Abstract:
In examples, a VM may receive and aggregate a first attestation report corresponding to a CPU and a second attestation report corresponding to a GPU. The aggregated data may be provided to an attestation service, which may verify the attestation reports indicate a TCB is to include the VM and GPU state data and is to isolate the GPU state data and the VM from an untrusted host OS. Based at least on the TCB being verified, the VM may perform one or more operations using the TCB. The TCB may include a trusted hypervisor to isolate the VM and GPU state data within the GPU(s) from the untrusted host OS. The trusted hypervisor may prevent the host OS from accessing device memory assigned to the VM based at least on controlling an IOMMU and/or second-level address translation (SLAT) used to access the data.
Abstract:
In examples, properties of an execution environment may be verified for a game session to comply with security policies based at least on analyzing attestation reports generated using one or more host devices. Content items may be associated with the game session to indicate the verification for presentation with a live stream video of the game session, in a pre-recorded video of the game session, and/or in another user interface associated with the game session. A record of the verification may be stored in a database, and the database may be queried to display the content item and/or to determine whether the verification occurred. The attestation reports may include an attestation report(s) generated using an input device(s) used to capture user inputs for the game session, such as an input device used to control the game session and/or provide a video capture of the player during the game session.
Abstract:
In examples, trusted execution environments (TEE) are provided for an instance of a parallel processing unit (PPU) as PPU TEEs. Different instances of a PPU correspond to different PPU TEEs, and provide accelerated confidential computing to a corresponding TEE. The processors of each PPU instance have separate and isolated paths through the memory system of the PPU which are assigned uniquely to an individual PPU instance. Data in device memory of the PPU may be isolated and access controlled amongst the PPU instances using one or more hardware firewalls. A GPU hypervisor assigns hardware resources to runtimes and performs access control and context switching for the runtimes. A PPU instance uses a cryptographic key to protect data for secure communication. Compute engines of the PPU instance are prevented from writing outside of a protected memory region. Access to a write protected region in PPU memory is blocked from other computing devices and/or device instances.
Abstract:
In examples, a parallel processing unit (PPU) operates within a trusted execution environment (TEE) implemented using a central processing unit (CPU). A virtual machine (VM) executing within the TEE is provided access to the PPU by a hypervisor. However, data of an application executed by the VM is inaccessible to the hypervisor and other untrusted entities outside of the TEE. To protect the data in transit, the VM and the PPU may encrypt or decrypt the data for secure communication between the devices. To protect the data within the PPU, a protected memory region may be created in PPU memory where compute engines of the PPU are prevented from writing outside of the protected memory region. A write protect memory region is generated where access to the PPU memory is blocked from other computing devices and/or device instances.
Abstract:
Unified virtual memory (UVM) management techniques using page table sharing between user mode and kernel mode GPU address spaces and creating the notion of privileged level of data.
Abstract:
A method to render graphics on a computer system having a plurality of graphics-processing units (GPUs) includes the acts of instantiating an independent physical-memory allocator for each GPU, receiving a physical-memory allocation request from a graphics-driver process, and passing the request to one of the independent physical-memory allocators. The method also includes creating a local physical-memory descriptor to reference physical memory on the GPU associated with that physical-memory allocator, assigning a physical-memory handle to the local physical-memory descriptor, and returning the physical-memory handle to the graphics-driver process to fulfill a subsequent memory-map request from the graphics-driver process.