公开(公告)号：US11741015B2

公开(公告)日：2023-08-29

申请号：US17820870

申请日：2022-08-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F11/07 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F12/10 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/12 ,  G06F12/10 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US09830262B2

公开(公告)日：2017-11-28

申请号：US14133488

申请日：2013-12-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Brian Fahs

IPC: G06F12/08 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F12/08 ,  G06F11/3037 ,  G06F11/3442 ,  G06F11/3471 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/88 ,  G06F2212/205

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

公开(公告)号：US20150199280A1

公开(公告)日：2015-07-16

申请号：US14155278

申请日：2014-01-14

Applicant: NVIDIA Corporation

Inventor： Steven E. Molnar ,  Jay Kishora Gupta ,  James Leroy Deming ,  Samuel Hammond Duncan ,  Jeffrey Smith

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/682

Abstract: A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Abstract translation: 提供了一种用于实现虚拟地址的多级转换的系统和方法。 该方法包括以下步骤：在第一存储器管理单元处接收包括第一地址空间中的虚拟地址的存储器请求，翻译虚拟地址以在第二地址空间中生成第二虚拟地址，以及发送修改的存储器请求 包括第二虚拟地址到第二存储器管理单元。 第二存储器管理单元被配置为转换第二虚拟地址以在第三地址空间中生成物理地址。 物理地址与存储器中的位置相关联。

公开(公告)号：US20140281319A1

公开(公告)日：2014-09-18

申请号：US13843838

申请日：2013-03-15

Applicant: NVIDIA CORPORATION

Inventor： Jay Kishora Gupta ,  Jay S. Huang ,  Steven E. Molnar ,  Parthasarathy Sriram ,  James Leroy Deming

IPC: G06F21/60

CPC classification number: G06F21/60 ,  G06F12/1441 ,  G06F12/1458 ,  G06F21/85

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract translation: 提供了一种用于保护数据的系统和方法。 在操作中，接收到从存储器读取数据的请求。 此外，确定数据是否存储在存储器的预定部分中。 如果确定数据存储在存储器的预定部分中，则返回数据和保护信号以用于保护数据。 在本发明的某些实施例中，存储在存储器的预定部分中的数据可以被进一步处理和写入到存储器的预定部分。 在本发明的其它实施例中，这种处理可以包含存储在存储器的预定部分外部的未受保护的数据。

公开(公告)号：US11893423B2

公开(公告)日：2024-02-06

申请号：US16562367

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Sonata Gale Wen ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/50 ,  G06F9/38 ,  G06F1/3296 ,  G06F1/04

CPC classification number: G06F9/5061 ,  G06F1/04 ,  G06F1/3296 ,  G06F9/3877 ,  G06F9/5027

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US20230297696A1

公开(公告)日：2023-09-21

申请号：US18185654

申请日：2023-03-17

Applicant: NVIDIA Corporation

Inventor： Philip Rogers ,  Mark Overby ,  Vyas Venkataraman ,  Naveen Cherukuri ,  James Leroy Deming ,  Gobikrishna Dhanuskodi ,  Dwayne Swoboda ,  Lucien Dunning ,  Aruna Manjunatha ,  Aaron Jiricek ,  Mark Hairgrove ,  Michael Woodmansee

IPC: G06F21/60 ,  G06F9/455 ,  G06F21/57

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F21/575 ,  G06F2009/45587

Abstract: In examples, a parallel processing unit (PPU) operates within a trusted execution environment (TEE) implemented using a central processing unit (CPU). A virtual machine (VM) executing within the TEE is provided access to the PPU by a hypervisor. However, data of an application executed by the VM is inaccessible to the hypervisor and other untrusted entities outside of the TEE. To protect the data in transit, the VM and the PPU may encrypt or decrypt the data for secure communication between the devices. To protect the data within the PPU, a protected memory region may be created in PPU memory where compute engines of the PPU are prevented from writing outside of the protected memory region. A write protect memory region is generated where access to the PPU memory is blocked from other computing devices and/or device instances.

公开(公告)号：US11663036B2

公开(公告)日：2023-05-30

申请号：US16562359

申请日：2019-09-05

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Gregory Scott Palmer ,  Jonathon Stuart Ramsey Evans ,  Shailendra Singh ,  Samuel H. Duncan ,  Wishwesh Anil Gandhi ,  Lacky V. Shah ,  Eric Rock ,  Feiqi Su ,  James Leroy Deming ,  Alan Menezes ,  Pranav Vaidya ,  Praveen Joginipally ,  Timothy John Purcell ,  Manas Mandal

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

CPC classification number: G06F9/485 ,  G06F9/461 ,  G06T1/20

Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

公开(公告)号：US11487673B2

公开(公告)日：2022-11-01

申请号：US14055345

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/08 ,  G06F11/07 ,  G06F12/12 ,  G06F12/10

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US10133677B2

公开(公告)日：2018-11-20

申请号：US14133489

申请日：2013-12-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  John Mashey

IPC: G06F12/12 ,  G06F12/122 ,  G06F12/08 ,  G06F12/1009

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

公开(公告)号：US10037228B2

公开(公告)日：2018-07-31

申请号：US13660763

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/1045 ,  G06F12/109

CPC classification number: G06F9/5027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.