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公开(公告)号：US20250046003A1
公开(公告)日：2025-02-06
申请号：US18921368
申请日：2024-10-21
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Timo VIITANEN , Levi OLIVER
Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.
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公开(公告)号：US20240087211A1
公开(公告)日：2024-03-14
申请号：US17941578
申请日：2022-09-09
Applicant: NVIDIA Corporation
Inventor： Greg MUTHLER , John BURGESS , Magnus ANDERSSON , Timo VIITANEN , Levi OLIVER
CPC classification number: G06T15/06 , G06T15/005 , G06T17/005
Abstract: An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.
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公开(公告)号：US20240095994A1
公开(公告)日：2024-03-21
申请号：US17946193
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005 , G06T15/40 , G06T2210/12 , G06T2210/21
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20230078932A1
公开(公告)日：2023-03-16
申请号：US17946828
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： John BURGESS , Gregory MUTHLER , Nikhil DIXIT , Henry MORETON , Yury URALSKY , Magnus ANDERSSON , Marco SALVI , Christoph KUBISCH
Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
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公开(公告)号：US20210390755A1
公开(公告)日：2021-12-16
申请号：US16897745
申请日：2020-06-10
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , James ROBERTSON , Magnus ANDERSSON
Abstract: Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.
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Patent Agency Ranking
公开(公告)号：US20240095993A1
公开(公告)日：2024-03-21
申请号：US17946093
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20230084570A1
公开(公告)日：2023-03-16
申请号：US17946221
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Henry Packard MORETON , Yury URALSKY , Levi OLIVER , Magnus ANDERSSON , Johannes DELIGIANNIS
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.
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公开(公告)号：US20230081791A1
公开(公告)日：2023-03-16
申请号：US17946515
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： John BURGESS , Gregory MUTHLER , Nikhil DIXIT , Henry MORETON , Yury URALSKY , Magnus ANDERSSON , Marco SALVI , Christoph KUBISCH
Abstract: A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.
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公开(公告)号：US20250104333A1
公开(公告)日：2025-03-27
申请号：US18971781
申请日：2024-12-06
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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公开(公告)号：US20240095995A1
公开(公告)日：2024-03-21
申请号：US17946201
申请日：2022-09-16
Applicant: NVIDIA Corporation
Inventor： Gregory MUTHLER , John BURGESS , Magnus ANDERSSON , Ian KWONG , Edward BIDDULPH
CPC classification number: G06T15/06 , G06T15/005 , G06T15/30 , G06T2210/12 , G06T2210/21
Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
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