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公开(公告)号：US09804885B2
公开(公告)日：2017-10-31
申请号：US15271171
申请日：2016-09-20
Applicant: NVIDIA Corporation
Inventor： Gerald F. Luiz , Philip Alexander Cuadra , Luke Durant , Shirish Gadre , Robert Ohannessian , Lacky V. Shah , Nicholas Wang , Arthur Merlin Danskin
CPC classification number: G06F9/461 , G06F9/4812 , G06F9/485
Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
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2.发明授权System, method, and computer program product for low latency scheduling and launch of memory defined tasks 有权用于低延迟调度和启动内存定义任务的系统，方法和计算机程序产品公开(公告)号：US09378139B2
公开(公告)日：2016-06-28
申请号：US13890178
申请日：2013-05-08
Applicant: NVIDIA Corporation
Inventor： Scott Ricketts , Brian Scott Pharris , Nicholas Wang , Luke David Durant , Philip Alexander Cuadra , Jerome F. Duluk, Jr.
CPC classification number: G06F12/0804 , G06F9/4843 , G06F12/0802
Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.
Abstract translation: 一种用于低延迟调度和启动内存定义任务的系统，方法和计算机程序产品。 该方法包括以下步骤：接收要存储在与处理器相关联的存储器中的任务元数据数据结构，将任务元数据结构发送到处理器的调度单元，将任务元数据结构存储在包括在该处理器中的高速缓存单元中 调度单元，以及将任务元数据结构从高速缓存单元复制到存储器。
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3.发明授权公开(公告)号：US09448837B2
公开(公告)日：2016-09-20
申请号：US13863286
申请日：2013-04-15
Applicant: NVIDIA CORPORATION
Inventor： Gerald F. Luiz , Philip Alexander Cuadra , Luke Durant , Shirish Gadre , Robert Ohannessian , Lacky V. Shah , Nicholas Wang , Arthur Merlin Danskin
CPC classification number: G06F9/461 , G06F9/4812 , G06F9/485
Abstract: Techniques are provided for restoring thread groups in a cooperative thread array (CTA) within a processing core. Each thread group in the CTA is launched to execute a context restore routine. Each thread group, executes the context restore routine to restore from a memory a first portion of context associated with the thread group, and determines whether the thread group completed an assigned function prior to executing the context restore routine. If the thread group completed an assigned function prior to executing the context restore routine, then the thread group exits the context restore routine. If the thread group did not complete the assigned function prior to executing the context restore routine, then the thread group executes one or more operations associated with a trap handler routine. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
Abstract translation: 提供了用于在处理核心内的协作线程数组（CTA）中恢复线程组的技术。 启动CTA中的每个线程组以执行上下文恢复例程。 每个线程组，执行上下文恢复例程以从存储器恢复与线程组相关联的上下文的第一部分，并且在执行上下文恢复例程之前确定线程组是否完成了分配的功能。 如果线程组在执行上下文恢复例程之前完成了分配的函数，则线程组将退出上下文恢复例程。 如果线程组在执行上下文恢复例程之前未完成分配的函数，则线程组将执行与陷阱处理程序例程相关联的一个或多个操作。 所公开技术的一个优点是陷阱处理例程在并行处理器中有效地操作。
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公开(公告)号：US10289418B2
公开(公告)日：2019-05-14
申请号：US13728784
申请日：2012-12-27
Applicant: NVIDIA CORPORATION
Inventor： Gerald F. Luiz , Philip Alexander Cuadra , Luke Durant , Shirish Gadre , Robert Ohannessian , Lacky V. Shah , Nicholas Wang , Arthur Danskin
Abstract: Techniques are provided for handling a trap encountered in a thread that is part of a thread array that is being executed in a plurality of execution units. In these techniques, a data structure with an identifier associated with the thread is updated to indicate that the trap occurred during the execution of the thread array. Also in these techniques, the execution units execute a trap handling routine that includes a context switch. The execution units perform this context switch for at least one of the execution units as part of the trap handling routine while allowing the remaining execution units to exit the trap handling routine before the context switch. One advantage of the disclosed techniques is that the trap handling routine operates efficiently in parallel processors.
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公开(公告)号：US20170249152A1
公开(公告)日：2017-08-31
申请号：US15594516
申请日：2017-05-12
Applicant: NVIDIA Corporation
Inventor： Philip Alexander Cuadra , Christopher Lamb , Lacky V. Shah
IPC: G06F9/38
Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.
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Patent Agency Ranking
公开(公告)号：US20170249151A1
公开(公告)日：2017-08-31
申请号：US15594515
申请日：2017-05-12
Applicant: NVIDIA Corporation
Inventor： Philip Alexander Cuadra , Christopher Lamb , Lacky V. Shah
IPC: G06F9/38
Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.
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7.发明申请SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR LOW LATENCY SCHEDULING AND LAUNCH OF MEMORY DEFINED TASKS 有权系统，方法和计算机程序产品，用于低时间调度和启动存储器定义的任务公开(公告)号：US20140337569A1
公开(公告)日：2014-11-13
申请号：US13890178
申请日：2013-05-08
Applicant: NVIDIA CORPORATION
Inventor： Scott Ricketts , Brian Scott Pharris , Nicholas Wang , Luke David Durant , Philip Alexander Cuadra , Jerome F. Duluk, Jr.
IPC: G06F12/08 , G11C11/406
CPC classification number: G06F12/0804 , G06F9/4843 , G06F12/0802
Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.
Abstract translation: 一种用于低延迟调度和启动内存定义任务的系统，方法和计算机程序产品。 该方法包括以下步骤：接收要存储在与处理器相关联的存储器中的任务元数据数据结构，将任务元数据结构发送到处理器的调度单元，将任务元数据结构存储在包括在该处理器中的高速缓存单元中 调度单元，以及将任务元数据结构从高速缓存单元复制到存储器。
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公开(公告)号：US10915364B2
公开(公告)日：2021-02-09
申请号：US15368434
申请日：2016-12-02
Applicant: Nvidia Corporation
Inventor： Stephen Jones , Philip Alexander Cuadra , Daniel Elliot Wexler , Ignacio Llamas , Lacky V. Shah , Jerome F. Duluk , Christopher Lamb
Abstract: Apparatuses, systems, and techniques for performing nested kernel execution within a parallel processing subsystem. In at least one embodiment, a parent thread launches a nested child grid on the parallel processing subsystem, and enables the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid.
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公开(公告)号：US10552202B2
公开(公告)日：2020-02-04
申请号：US15594516
申请日：2017-05-12
Applicant: NVIDIA Corporation
Inventor： Philip Alexander Cuadra , Christopher Lamb , Lacky V. Shah
Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.
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公开(公告)号：US10095542B2
公开(公告)日：2018-10-09
申请号：US15798174
申请日：2017-10-30
Applicant: NVIDIA Corporation
Inventor： Gerald F. Luiz , Philip Alexander Cuadra , Luke Durant , Shirish Gadre , Robert Ohannessian , Lacky V. Shah , Nicholas Wang , Arthur Merlin Danskin
Abstract: Techniques are provided for restoring threads within a processing core. The techniques include, for a first thread group included in a plurality of thread groups, executing a context restore routine to restore from a memory a first portion of a context associated with the first thread group, determining whether the first thread group completed an assigned function, and, if the first thread group completed the assigned function, then exiting the context restore routine, or if the first thread group did not complete the assigned function, then executing one or more operations associated with a trap handler routine.
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