公开(公告)号：US09153958B2

公开(公告)日：2015-10-06

申请号：US13968337

申请日：2013-08-15

Applicant: NXP B.V.

Inventor： Gijs de Raad ,  Paul Cappon ,  Albert Jan Huitsing

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02 ,  H03K19/003

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H03K19/00315

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Abstract translation: 描述了静电放电（ESD）保护装置的实施例和操作ESD保护装置的方法。 在一个实施例中，用于集成电路（IC）装置的ESD保护装置包括被配置为在ESD事件期间传导ESD电流的大FET，以及被配置为在ESD事件期间触发大电容器的触发装置。 触发装置包括被配置为检测ESD事件的转换速率检测器，被配置为驱动大FET的驱动器级以及保持驱动级接通以将驱动级导通以驱动大FET的栅极端的驱动电压的保持锁存器 这对于bigFET的漏极端子或源极端子的预偏置不敏感。 还描述了其它实施例。

公开(公告)号：US20150049403A1

公开(公告)日：2015-02-19

申请号：US13968337

申请日：2013-08-15

Applicant: NXP B.V.

Inventor： Gijs de Raad ,  Paul Cappon ,  Albert Jan Huitsing

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0285 ,  H03K19/00315

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Abstract translation: 描述了静电放电（ESD）保护装置的实施例和操作ESD保护装置的方法。 在一个实施例中，用于集成电路（IC）装置的ESD保护装置包括被配置为在ESD事件期间传导ESD电流的大FET，以及被配置为在ESD事件期间触发大电容器的触发装置。 触发装置包括被配置为检测ESD事件的转换速率检测器，被配置为驱动大FET的驱动器级以及保持驱动级接通以将驱动级导通以驱动大FET的栅极端的驱动电压的保持锁存器 这对于bigFET的漏极端子或源极端子的预偏置不敏感。 还描述了其它实施例。

公开(公告)号：US09653447B2

公开(公告)日：2017-05-16

申请号：US14495468

申请日：2014-09-24

Applicant: NXP B.V.

Inventor： Albert Jan Huitsing ,  Jan Claes

IPC: H01L29/10 ,  H01L27/02 ,  H01L27/082 ,  H01L23/535 ,  H01L23/367 ,  H01L27/12 ,  H01L21/8222 ,  H01L29/417

CPC classification number: H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

公开(公告)号：US20160086934A1

公开(公告)日：2016-03-24

申请号：US14495468

申请日：2014-09-24

Applicant: NXP B.V.

Inventor： Albert Jan Huitsing ,  Jan Claes

IPC: H01L27/02 ,  H01L21/8222 ,  H01L23/367 ,  H01L27/12 ,  H01L27/082 ,  H01L23/535

CPC classification number: H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

Abstract translation: 公开了一种PNP ESD集成电路，包括：衬底，形成在衬底内的有源区，有源区包括至少一个第二导电类型的基极区;多个第一导电类型的集电极区，形成在有源区内 ，在有源区内形成的第一导电类型的多个发射极区域和与多个发射极区域和多个集电极区域接触的局部互连层（LIL），LIL包括形成在集电区域上的冷却翅片触点， 提升收集区目前的处理能力。