公开(公告)号：US10763888B1

公开(公告)日：2020-09-01

申请号：US16407501

申请日：2019-05-09

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

Abstract: A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.

公开(公告)号：US10439633B2

公开(公告)日：2019-10-08

申请号：US15926442

申请日：2018-03-20

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Muhammed Bolatkale ,  Chenming Zhang

IPC: H03M3/00

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

公开(公告)号：US20210126648A1

公开(公告)日：2021-04-29

申请号：US17065731

申请日：2020-10-08

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M3/00

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

公开(公告)号：US11463101B2

公开(公告)日：2022-10-04

申请号：US17158913

申请日：2021-01-26

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M3/00

Abstract: The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.

公开(公告)号：US11658677B2

公开(公告)日：2023-05-23

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/08

CPC classification number: H03M3/34 ,  H03M1/0626 ,  H03M1/0854 ,  H03M3/32 ,  H03M3/364 ,  H03M3/38

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US20230102232A1

公开(公告)日：2023-03-30

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/06

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US11606102B2

公开(公告)日：2023-03-14

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US20220416809A1

公开(公告)日：2022-12-29

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US11271585B2

公开(公告)日：2022-03-08

申请号：US17065731

申请日：2020-10-08

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Lucien Johannes Breems ,  Muhammed Bolatkale

IPC: H03M3/00

Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.