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公开(公告)号：US20230370031A1
公开(公告)日：2023-11-16
申请号：US18316325
申请日：2023-05-12
Applicant: NXP B.V.
Inventor： Sundeep Lakshmana Javvaji , Muhammed Bolatkale , Lucien Johannes Breems , Kofi Afolabi Anthony Makinwa
CPC classification number: H03F3/387 , H03F1/26 , H03F2200/372
Abstract: A chopper circuit (100) for a multipath chopper amplifier (201) is described. The chopper circuit (100) comprises a first chopper device (110) in a first circuit path (111), wherein the first chopper device (110) is configured to be controlled by a first clock signal (315), which has a first frequency; and a second chopper device (120) in a second circuit path (121), parallel to the first circuit path (111), wherein the second chopper device (120) is configured to be controlled by a second clock signal (325), which has a second frequency, wherein the first frequency is greater than the second frequency. Furthermore, a corresponding method of chopping an input signal (102) is described.
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公开(公告)号：US20230238974A1
公开(公告)日：2023-07-27
申请号：US18061601
申请日：2022-12-05
Applicant: NXP B.V.
Inventor： Robert Rutten , Muhammed Bolatkale , Lucien Johannes Breems
CPC classification number: H03M1/0621 , H03M1/1047 , H03M1/181
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.
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公开(公告)号：US11522557B1
公开(公告)日：2022-12-06
申请号：US17388157
申请日：2021-07-29
Applicant: NXP B.V.
Inventor： Robert Rutten , Martin Kessel , Hendrik van der Ploeg , Lucien Johannes Breems , Muhammed Bolatkale , Evert-Jan Pol , Manfred Zupke , Bernard Burdiek , Johannes Hubertus Antonius Brekelmans , Shagun Bajoria
IPC: H03M3/00
Abstract: A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.
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公开(公告)号：US20170150521A1
公开(公告)日：2017-05-25
申请号：US15356451
申请日：2016-11-18
Applicant: NXP B.V.
Inventor： Jan Niehof , Shagun Bajoria , Muhammed Bolatkale , Robert Rutten , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans
CPC classification number: H04W74/002 , H03M1/0678 , H03M1/08 , H03M1/123 , H03M1/183 , H04L5/0051
Abstract: A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node.
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公开(公告)号：US11555901B2
公开(公告)日：2023-01-17
申请号：US16939875
申请日：2020-07-27
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Dongjin Son , Maxim Kulesh
IPC: G01S7/48 , G01S7/4865 , G01S7/4863 , H01L31/107
Abstract: Example aspects are directed to operating a SPAD receiver such as may be used in a light detection and ranging (Lidar) system. In one example, the SPAD receiver has SPAD circuitry for multiple photon detections using a single-channel TDC (time-to-digital converter), and such photon detection is quenched after detection so as to establish an effective pre-defined OFF period. In response, the SPAD circuitry is recharged for a subsequent ON period during which the SPAD circuitry is unquenched (or armed) for further photon detection and processing.
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Patent Agency Ranking
公开(公告)号：US20220026543A1
公开(公告)日：2022-01-27
申请号：US16939875
申请日：2020-07-27
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Dongjin Son , Maxim Kulesh
IPC: G01S7/4865 , H01L31/107 , G01S7/4863
Abstract: Example aspects are directed to operating a SPAD receiver such as may be used in a light detection and ranging (Lidar) system. In one example, the SPAD receiver has SPAD circuitry for multiple photon detections using a single-channel TDC (time-to-digital converter), and such photon detection is quenched after detection so as to establish an effective pre-defined OFF period. In response, the SPAD circuitry is recharged for a subsequent ON period during which the SPAD circuitry is unquenched (or armed) for further photon detection and processing.
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7.发明授权公开(公告)号：US10763888B1
公开(公告)日：2020-09-01
申请号：US16407501
申请日：2019-05-09
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
Abstract: A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.
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公开(公告)号：US10541699B1
公开(公告)日：2020-01-21
申请号：US16157355
申请日：2018-10-11
Applicant: NXP B.V.
Inventor： Robert Rutten , Massimo Ciacci , Manfred Zupke , Lucien Johannes Breems , Johannes Hubertus Antonius Brekelmans , Muhammed Bolatkale , Shagun Bajoria , Soheil Bahrami
Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.
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公开(公告)号：US10439633B2
公开(公告)日：2019-10-08
申请号：US15926442
申请日：2018-03-20
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale , Chenming Zhang
IPC: H03M3/00
Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.
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公开(公告)号：US20240048150A1
公开(公告)日：2024-02-08
申请号：US17880868
申请日：2022-08-04
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/354
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
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