公开(公告)号：US20230361781A1

公开(公告)日：2023-11-09

申请号：US18310184

申请日：2023-05-01

Applicant: NXP B.V.

Inventor： Muhammed Bolatkale ,  Lucien Johannes Breems ,  Pierluigi Cenci ,  Shagun Bajoria ,  Mohammed Abo Alainein

IPC: H03M1/14 ,  H03M1/66

CPC classification number: H03M1/14 ,  H03M1/662

Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising:



i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13);
ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and
iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to:
swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).

公开(公告)号：US12301249B2

公开(公告)日：2025-05-13

申请号：US18310184

申请日：2023-05-01

Applicant: NXP B.V.

Inventor： Muhammed Bolatkale ,  Lucien Johannes Breems ,  Pierluigi Cenci ,  Shagun Bajoria ,  Mohammed Abo Alainein

IPC: H03M1/14 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/66 ,  H03M1/74

Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising: i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13); ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to: swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).

公开(公告)号：US11658677B2

公开(公告)日：2023-05-23

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/08

CPC classification number: H03M3/34 ,  H03M1/0626 ,  H03M1/0854 ,  H03M3/32 ,  H03M3/364 ,  H03M3/38

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US20230102232A1

公开(公告)日：2023-03-30

申请号：US17490415

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Lucien Johannes Breems ,  Marcello Ganzerli ,  Chenming Zhang ,  Pierluigi Cenci

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/06

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

公开(公告)号：US11606102B2

公开(公告)日：2023-03-14

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

公开(公告)号：US20220416809A1

公开(公告)日：2022-12-29

申请号：US17449030

申请日：2021-09-27

Applicant: NXP B.V.

Inventor： Chenming Zhang ,  Marcello Ganzerli ,  Pierluigi Cenci ,  Lucien Johannes Breems

IPC: H03M3/00

Abstract: A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2nd filtered signal to a digital output signal by sampling at a predetermined sampling frequency(fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.