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公开(公告)号：US20170192446A1
公开(公告)日：2017-07-06
申请号：US14989378
申请日：2016-01-06
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula , Abhijeet Chandrakant Kulkarni , Kenneth Jaramillo
CPC classification number: G05F3/02 , G06F1/266 , G06F1/3253 , H02J4/00 , H04L12/10 , H04L43/08 , H04L43/16 , Y02D10/151 , Y02D50/20 , Y04S40/168
Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.
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公开(公告)号：US10019386B2
公开(公告)日：2018-07-10
申请号：US14705631
申请日：2015-05-06
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula
CPC classification number: G06F13/126 , G06F11/2247 , G06F11/3051 , G06F13/385
Abstract: One or more characteristics of devices are ascertained in accordance with one or more aspects of the disclosure. As may be consistent with one or more embodiments, the attachment of an external circuit to an input port is detected based on a resistance value presented by the external circuit. A resistance range that includes the resistance value presented at the input port is determined, in response to detecting the attachment, by dynamically coupling one or more of a plurality of resistor-based circuits relative to the input port. A signal presented by the external circuit on the input port is coded based on the determined resistance range, using one or more of the resistor-based circuits, and the code is used to identify a type of the external circuit. These aspects can provide for the communication of power and data with a variety of different types of external circuits.
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公开(公告)号：US20180095490A1
公开(公告)日：2018-04-05
申请号：US15821817
申请日：2017-11-23
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula , Abjijeet Chandrakant Kulkarni , Kenneth Jaramillo , Siamak Delshadpour , Xueyang Geng
CPC classification number: G05F3/02 , G06F1/266 , G06F1/3253 , H02J4/00 , H04L12/10 , H04L43/08 , H04L43/16 , Y02D10/151 , Y02D50/20 , Y04S40/168
Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.
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公开(公告)号：US10763830B2
公开(公告)日：2020-09-01
申请号：US16185639
申请日：2018-11-09
Applicant: NXP B.V.
Inventor： Siamak Delshadpour , Chiahung Su
Abstract: A temperature compensated current controlled oscillator (CCO) including a first current generator configured to produce a proportional to absolute temperature (PTAT) current based upon a trim signal, a second current generator configured to produce a complementary to absolute temperature (CTAT) current based upon a temperature measurement, and a ring oscillator configured to receive the PTAT current and the CTAT current and to produce a frequency signal based upon the PTAT current and the CTAT current.
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公开(公告)号：US09473130B2
公开(公告)日：2016-10-18
申请号：US14048689
申请日：2013-10-08
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula
CPC classification number: H03K5/22 , G06F1/02 , H02J7/0052 , H03K4/08 , H03K4/94
Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving providing a clock signal. As consistent with one or more embodiments herein, a sawtooth waveform signal is generated in a manner that facilitates low power operation. In some implementations, the sawtooth waveform signal is generated using an oscillator that operates without necessarily employing R-C circuits and/or without rail-to-rail voltage supply, such as via a nonlinear oscillator. The sawtooth waveform signal is used to generate a trapezoidal waveform signal, and a clock signal is generated using the trapeziodal waveform signal.
Abstract translation: 本公开的各个方面涉及涉及提供时钟信号的方法和装置。 与本文中的一个或多个实施例一致，以促进低功率操作的方式产生锯齿波形信号。 在一些实施方式中，锯齿波形信号是通过使用振荡器来产生的，所述振荡器例如通过非线性振荡器，不需要使用R-C电路和/或没有轨到轨电压供电。 锯齿波形信号用于产生梯形波形信号，并且使用梯形波形信号产生时钟信号。
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Patent Agency Ranking
公开(公告)号：US20150097516A1
公开(公告)日：2015-04-09
申请号：US14048689
申请日：2013-10-08
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula
CPC classification number: H03K5/22 , G06F1/02 , H02J7/0052 , H03K4/08 , H03K4/94
Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving providing a clock signal. As consistent with one or more embodiments herein, a sawtooth waveform signal is generated in a manner that facilitates low power operation. In some implementations, the sawtooth waveform signal is generated using an oscillator that operates without necessarily employing R-C circuits and/or without rail-to-rail voltage supply, such as via a nonlinear oscillator. The sawtooth waveform signal is used to generate a trapezoidal waveform signal, and a clock signal is generated using the trapeziodal waveform signal.
Abstract translation: 本公开的各个方面涉及涉及提供时钟信号的方法和装置。 与本文中的一个或多个实施例一致，以促进低功率操作的方式产生锯齿波形信号。 在一些实施方式中，锯齿波形信号是通过使用振荡器来产生的，所述振荡器例如通过非线性振荡器，不需要使用R-C电路和/或没有轨到轨电压供电。 锯齿波形信号用于产生梯形波形信号，并且使用梯形波形信号产生时钟信号。
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公开(公告)号：US10209730B2
公开(公告)日：2019-02-19
申请号：US15821817
申请日：2017-11-23
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula , Abjijeet Chandrakant Kulkarni , Kenneth Jaramillo , Siamak Delshadpour , Xueyang Geng
IPC: H01H35/00 , H01H83/00 , H02H3/00 , H01H47/00 , G05F3/02 , H02J4/00 , G06F1/26 , H04L12/10 , H04L12/26
Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.
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公开(公告)号：US09568926B2
公开(公告)日：2017-02-14
申请号：US14499999
申请日：2014-09-29
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Vemula , Siamak Delshadpour
Abstract: Aspects of the present disclosure are directed to circuits, apparatuses, and methods for power management. According to an example embodiment, an apparatus includes a low drop-out (LDO) voltage-regulation circuit configured to generate a regulated voltage from a voltage provided to a supply terminal of the LDO voltage-regulation circuit. The apparatus also includes switching circuitry coupled to the LDO voltage-regulation circuit and to a plurality of voltage sources. The voltage sources include at least power line carried along with a data bus and another voltage source. Each of the plurality of voltage sources provides a respectively different voltage range. The switching circuitry is configured, in response to a power-related condition of the plurality of voltage sources and while maintaining power to the LDO voltage-regulation circuit, to select and couple one of the voltage sources to the supply terminal and uncouple other ones of voltage sources from the supply terminal.
Abstract translation: 本公开的方面涉及用于电力管理的电路，装置和方法。 根据示例性实施例，一种装置包括：低压降（LDO）电压调节电路，被配置为从提供给LDO稳压电路的电源端的电压产生调节电压。 该装置还包括耦合到LDO电压调节电路和多个电压源的开关电路。 电压源至少包括与数据总线和另一个电压源一起携带的电力线。 多个电压源中的每一个提供分别不同的电压范围。 开关电路被配置为响应于多个电压源的功率相关状况并且在保持对LDO电压调节电路的电力的同时，选择并将一个电压源耦合到电源端子并将其它 供电端子的电压源。
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公开(公告)号：US20160328337A1
公开(公告)日：2016-11-10
申请号：US14705631
申请日：2015-05-06
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Mohan Reddy Vemula
CPC classification number: G06F13/126 , G06F11/2247 , G06F11/3051 , G06F13/385
Abstract: One or more characteristics of devices are ascertained in accordance with one or more aspects of the disclosure. As may be consistent with one or more embodiments, the attachment of an external circuit to an input port is detected based on a resistance value presented by the external circuit. A resistance range that includes the resistance value presented at the input port is determined, in response to detecting the attachment, by dynamically coupling one or more of a plurality of resistor-based circuits relative to the input port. A signal presented by the external circuit on the input port is coded based on the determined resistance range, using one or more of the resistor-based circuits, and the code is used to identify a type of the external circuit. These aspects can provide for the communication of power and data with a variety of different types of external circuits.
Abstract translation: 根据本公开的一个或多个方面来确定装置的一个或多个特征。 可以与一个或多个实施例一致，基于由外部电路呈现的电阻值来检测外部电路到输入端口的附着。 响应于检测到附件，通过动态地耦合多个基于电阻器的电路中的一个或多个相对于输入端口来确定包括在输入端口处呈现的电阻值的电阻范围。 基于所确定的电阻范围，使用一个或多个基于电阻器的电路对由输入端口上的外部电路呈现的信号进行编码，并且该代码用于识别外部电路的类型。 这些方面可以提供电力和数据与各种不同类型的外部电路的通信。
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公开(公告)号：US20160091907A1
公开(公告)日：2016-03-31
申请号：US14499999
申请日：2014-09-29
Applicant: NXP B.V.
Inventor： Chiahung Su , Madan Vemula , Siamak Delshadpour
IPC: G05F1/56
Abstract: Aspects of the present disclosure are directed to circuits, apparatuses, and methods for power management. According to an example embodiment, an apparatus includes a low drop-out (LDO) voltage-regulation circuit configured to generate a regulated voltage from a voltage provided to a supply terminal of the LDO voltage-regulation circuit. The apparatus also includes switching circuitry coupled to the LDO voltage-regulation circuit and to a plurality of voltage sources. The voltage sources include at least power line carried along with a data bus and another voltage source. Each of the plurality of voltage sources provides a respectively different voltage range. The switching circuitry is configured, in response to a power-related condition of the plurality of voltage sources and while maintaining power to the LDO voltage-regulation circuit, to select and couple one of the voltage sources to the supply terminal and uncouple other ones of voltage sources from the supply terminal.
Abstract translation: 本公开的方面涉及用于电力管理的电路，装置和方法。 根据示例性实施例，一种装置包括：低压降（LDO）电压调节电路，被配置为从提供给LDO电压调节电路的电源端的电压产生调节电压。 该装置还包括耦合到LDO电压调节电路和多个电压源的开关电路。 电压源至少包括与数据总线和另一个电压源一起携带的电力线。 多个电压源中的每一个提供分别不同的电压范围。 开关电路被配置为响应于多个电压源的功率相关状况并且在保持对LDO电压调节电路的电力的同时，选择并将一个电压源耦合到电源端子并将其它 供电端子的电压源。
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