公开(公告)号：US11228314B1

公开(公告)日：2022-01-18

申请号：US17080791

申请日：2020-10-26

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xueyang Geng

IPC: H03K19/0175 ,  H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K17/16

Abstract: A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

公开(公告)号：US20200161986A1

公开(公告)日：2020-05-21

申请号：US16193199

申请日：2018-11-16

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Madan Mohan Reddy Vemula ,  Alma Anderson

IPC: H02M7/217

Abstract: A low voltage drop rectifier is provided. The rectifier includes a diode having a first terminal coupled at an input node and a second terminal coupled at an output node. A first transistor having a first current electrode is coupled at the input node and a second current electrode is coupled at the output node. A comparator having a first input is coupled at the input node, a second input is coupled at the output node, and an output is coupled to a control electrode of the first transistor. A bias circuit is coupled to the comparator circuit and is configured to generate a bias current in the comparator.

公开(公告)号：US20200153395A1

公开(公告)日：2020-05-14

申请号：US16184921

申请日：2018-11-08

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Siamak Delshadpour ,  Soon-Gil Jung ,  Ahmad Yazdi

IPC: H03F3/19 ,  H03D7/14 ,  H03K5/003

Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

公开(公告)号：US10917055B2

公开(公告)日：2021-02-09

申请号：US16184921

申请日：2018-11-08

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Siamak Delshadpour ,  Soon-Gil Jung ,  Ahmad Yazdi

IPC: H03F3/45 ,  H03F3/19 ,  H03K5/003 ,  H03D7/14

Abstract: A wide band communications circuit buffer can include a pair of NPN bipolar transistor emitter followers deployed as a voltage buffer and disposed at inputs before and outputs after an equalization module, and a pair of diode connected NPN transistors deployed as a level shifter and disposed following the emitter followers before an output of the wide band driver to keep an output level at the output of the wide band buffer close to a desired level. Resistors connected between emitters and a VEE terminal can be used to further adjust the DC level. An LC tank filter can be provided between emitters of the voltage buffer components and the circuit's outputs to pass and boost high frequency signals provided to next stage components. The wide band buffer is, inter alia, appropriate for use in providing a DC level shift function as used in wired data communication systems circuitry.

公开(公告)号：US10862720B2

公开(公告)日：2020-12-08

申请号：US16154196

申请日：2018-10-08

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xueyang Geng ,  Ahmad Yazdi

IPC: H04L27/152 ,  H03K5/24 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107 ,  H04B1/10 ,  H03K5/08

Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

公开(公告)号：US10209730B2

公开(公告)日：2019-02-19

申请号：US15821817

申请日：2017-11-23

Applicant: NXP B.V.

Inventor： Chiahung Su ,  Madan Mohan Reddy Vemula ,  Abjijeet Chandrakant Kulkarni ,  Kenneth Jaramillo ,  Siamak Delshadpour ,  Xueyang Geng

IPC: H01H35/00 ,  H01H83/00 ,  H02H3/00 ,  H01H47/00 ,  G05F3/02 ,  H02J4/00 ,  G06F1/26 ,  H04L12/10 ,  H04L12/26

Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

公开(公告)号：US10910998B2

公开(公告)日：2021-02-02

申请号：US16135224

申请日：2018-09-19

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Ahmad Yazdi ,  Xueyang Geng

IPC: H03C3/09 ,  H04B1/10 ,  H03L7/099 ,  H03L7/089 ,  H03G3/34 ,  H03K5/24 ,  H03H11/12 ,  H04B17/11 ,  H04B1/16 ,  H04B17/21 ,  H04B1/04 ,  H04B1/405

Abstract: Various embodiments relate to a method for calibration of a center frequency of a BPF in an FSK transceiver, the method including the steps of filtering a carrier frequency signal by the BPF to produce a filtered signal, detecting, by a phase-frequency detector (“PFD”), a difference in phase between the carrier frequency signal and the filtered signal from the BPF, sweeping a calibration code of the BPF, detecting a transition in the sign of the phase difference and capturing a calibration code associated with the transition in the sign of the phase difference for calibration of the BPF.

公开(公告)号：US10003192B2

公开(公告)日：2018-06-19

申请号：US14868044

申请日：2015-09-28

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Ahmad Yazdi ,  Siamak Delshadpour ,  Abhijeet Chandrakant Kulkarni

IPC: H02J1/10 ,  H02J3/38 ,  H02J1/00 ,  H02M7/04

CPC classification number: H02J1/00 ,  H02M7/04

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

公开(公告)号：US20170093154A1

公开(公告)日：2017-03-30

申请号：US14868044

申请日：2015-09-28

Applicant: NXP B.V.

Inventor： Xueyang Geng ,  Ahmad Yazdi ,  Siamak Delshadpour ,  Abhijeet Chandrakant Kulkarni

IPC: H02J1/00 ,  H02M7/04

CPC classification number: H02J1/00 ,  H02M7/04

Abstract: A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

公开(公告)号：US10429874B1

公开(公告)日：2019-10-01

申请号：US16228420

申请日：2018-12-20

Applicant: NXP B.V.

Inventor： Siamak Delshadpour ,  Xueyang Geng

IPC: G11C5/14 ,  G05F3/24 ,  H03F3/45 ,  H02M3/07

Abstract: A reference voltage circuit with current buffer including a low voltage reference to output a low voltage, a first resistor-capacitor (RC) filter to filter the low voltage, a buffer circuit to output a current to be used by a load, a second RC filter associated with the load, and a capacitor in parallel with the buffer circuit configured to increase a rise time of the buffer.