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公开(公告)号：US20230008852A1
公开(公告)日：2023-01-12
申请号：US17809978
申请日：2022-06-30
Applicant: NXP B.V.
Abstract: A transmission line. The transmission line includes a reference electrode. The transmission line also includes a stripline. The stripline meanders within a plane. The stripline has a non-planar profile when viewed along a direction parallel to the plane.
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公开(公告)号：US20240098906A1
公开(公告)日：2024-03-21
申请号：US18459759
申请日：2023-09-01
Applicant: NXP B.V.
Inventor： Xin Yang , Mustafa Acar , Zhe Chen , Dominicus MARTINUS WILHELMUS Leenaerts
CPC classification number: H05K3/3405 , H05K1/0233 , H05K1/025 , H05K2201/10053
Abstract: A circuit comprising: a digital attenuator part comprising: a first and second attenuator terminal; a first inductor having a first terminal coupled to the first attenuator terminal and a second terminal coupled to the second attenuator terminal; a first switched arrangement comprising a first switch having a first switch-terminal and a second switch-terminal, wherein the first switch-terminal is coupled to the first terminal of the first inductor, and a first resistor and a first capacitor are arranged in parallel, coupled between the second switch-terminal and a reference voltage; and a second switched arrangement comprising a second switch having a first switch-terminal and a second switch-terminal, wherein the first switch-terminal is coupled to the second terminal of the first inductor, and wherein a second resistor and a second capacitor are arranged in parallel and coupled between the second switch-terminal and the reference voltage.
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Patent Agency Ranking
公开(公告)号：US20220311137A1
公开(公告)日：2022-09-29
申请号：US17651832
申请日：2022-02-21
Applicant: NXP B.V.
Inventor： Jan Willem Bergman , Mustafa Acar , Antonius Hendrikus Jozef Kamphuis , Dominicus MARTINUS WILHELMUS Leenaerts , Rajesh Mandamparambil , Paul Mattheijssen
Abstract: An integrated circuit comprising a package, phased antenna array and die. The die comprises a plurality of unit cells, wherein each unit cell is divided into quadrants. Each quadrant comprises a receiver terminal located on a first axis, and a transmitter terminal located on a second axis, wherein the first axis is orthogonal to the second axis, and there is mirror symmetry between the nearest neighbour quadrants in the unit cell. The package comprises a plurality of pairs of feed lines, each pair of feed lines comprising a receiver feed line and a transmitter feed line. The receiver feed line is connected to one of the receiver terminals and the transmitter feed line is connected to the transmitter terminal in the same die quadrant. The receiver feed line is orthogonal to the transmitter feed line. Each antenna element is coupled to a respective pair of feed lines.
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公开(公告)号：US20240388259A1
公开(公告)日：2024-11-21
申请号：US18638786
申请日：2024-04-18
Applicant: NXP B.V.
Inventor： Xin Yang , Stephane David , Mark Pieter van der Heijden , Dominicus MARTINUS WILHELMUS Leenaerts
Abstract: A bias circuit for a RF amplifier is described. The bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. An output of the bias circuit is coupled to the second transistor second terminal. A second current mirror coupled to the first current mirror and the bias circuit output. The bias circuit includes a first resistor coupled between a first transistor control terminal and a second transistor control terminal and a variable capacitor coupled between the second transistor control terminal and a ground.
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5.发明公开公开(公告)号：US20240106101A1
公开(公告)日：2024-03-28
申请号：US18459815
申请日：2023-09-01
Applicant: NXP B.V.
Inventor： Xin Yang , Mustafa Acar , Zhe Chen , Dominicus MARTINUS WILHELMUS Leenaerts
IPC: H01P5/12
CPC classification number: H01P5/12
Abstract: A circuit comprising: a common terminal, first terminal and second terminal, wherein the common terminal is coupled to a first and second circuit branch at a branch node; wherein the first/second circuit branches include a respective first/second quarter wavelength transmission line having a first end coupled to the branch node and a second end respectively coupled to the first/second terminal; wherein the first and second terminals are coupled together via a branch-interconnection arrangement; wherein the circuit comprises: a first switched arrangement comprising a first switch having a first and second switch-terminal, wherein the first switch-terminal is coupled to the common terminal, and wherein a first resistor and a first capacitor are arranged in parallel and coupled between the second switch-terminal and a reference terminal; and a second switched arrangement coupled to the first terminal, wherein the first quarter wavelength transmission line is coupled between the first and second switched arrangements.
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公开(公告)号：US20240388254A1
公开(公告)日：2024-11-21
申请号：US18638806
申请日：2024-04-18
Applicant: NXP B.V.
Inventor： Xin Yang , Stephane David , Mark Pieter van der Heijden , Dominicus MARTINUS WILHELMUS Leenaerts
Abstract: A bias circuit includes a first transistor and a second transistor configured as a first current mirror. A first current source is arranged between a supply node and the first transistor first terminal. A bias circuit output is coupled to the second transistor second terminal. A second current mirror is coupled to the first current mirror and the bias circuit output. A second current source is arranged between the supply node and the second current mirror. A third transistor in a diode-connected configuration is coupled between the first transistor second terminal and a ground. Alternatively or in addition, the bias circuit includes a first variable capacitor coupled between the second transistor first terminal and the second transistor second terminal. A fourth transistor has a control terminal coupled to the supply node, a first terminal coupled to the supply node and a second terminal coupled to the second transistor first terminal.
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公开(公告)号：US20230170871A1
公开(公告)日：2023-06-01
申请号：US18051596
申请日：2022-11-01
Applicant: NXP B.V.
Inventor： Xin Yang , Dominicus MARTINUS WILHELMUS Leenaerts , Rana Azhar Shaheen
CPC classification number: H03H7/255 , H03F3/19 , H03F2200/451
Abstract: An attenuation circuit comprising: a connection-node for connecting to an RF connection; an isolation-capacitor connected in series between the connection-node and an internal-node; a first-bias-resistor connected in series between a first-control-node and the internal-node; a second-bias-resistor connected in series between the internal-node and a second-control-node; a first-attenuation-diode connected in series between the first-control-node and the internal-node, wherein the anode of the first-attenuation-diode is closest to the first-control-node; a second-attenuation-diode connected in series between the internal-node and the second-control-node, wherein the anode of the second-attenuation-diode is closest to the internal-node; a first-decoupling-capacitor connected in series between the first-control-node and the reference-node; and a second-decoupling-capacitor connected in series between the second-control-node and the reference-node.
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