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公开(公告)号：US12081371B2
公开(公告)日：2024-09-03
申请号：US18059595
申请日：2022-11-29
Applicant: NXP B.V.
Inventor： Cornelis Klaas Waardenburg , Johannes Petrus Antonius Frambach , Stefan Paul van den Hoek , Rinke de Jong
CPC classification number: H04L25/0276 , H03F3/45511 , H04L12/40 , H04L2012/40215
Abstract: An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.
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公开(公告)号：US11061844B2
公开(公告)日：2021-07-13
申请号：US15905061
申请日：2018-02-26
Applicant: NXP B.V.
Inventor： Clemens Gerhardus Johannes de Haas , Johannes Petrus Antonius Frambach , Thomas John William Donaldson
Abstract: The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.
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公开(公告)号：US20240120956A1
公开(公告)日：2024-04-11
申请号：US18463174
申请日：2023-09-07
Applicant: NXP B.V.
Inventor： Johannes Petrus Antonius Frambach , Cornelis Klaas Waardenburg , Stefan Paul van den Hoek , Gerard Arie de Wit
CPC classification number: H04B1/04 , H04L12/40 , H04L2012/40215
Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.
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公开(公告)号：US11843388B2
公开(公告)日：2023-12-12
申请号：US17647739
申请日：2022-01-12
Applicant: NXP B.V.
CPC classification number: H03L7/0991 , G11C7/1036 , G11C7/16 , H03L7/081 , H03L7/085
Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).
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公开(公告)号：US10790873B2
公开(公告)日：2020-09-29
申请号：US16206541
申请日：2018-11-30
Applicant: NXP B.V.
Inventor： Sujan Pandey , Johannes Petrus Antonius Frambach
Abstract: The present application relates to a transceiver, TX/RX PHY, and a method of operating the TX/RX PHY arranged for bi-directional data communication of a node with a counterpart node connected to in a point-to-point network using differential mode signaling over a single twisted-pair cable. A TX adjustment component is arranged in a TX path of the TX/RX PHY and configured to adjust a TX data communication signal generated by the TX/RX PHY for transmittal to the counterpart node. The TX adjustment component is further configured to accept information about a common mode signal detected on the single twisted-pair cable and to adjust the TX data communication signal to at least weaken the common mode signal occurring at the counterpart node in response to transmitting the TX data communication signal.
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Patent Agency Ranking
公开(公告)号：US20180260353A1
公开(公告)日：2018-09-13
申请号：US15905061
申请日：2018-02-26
Applicant: NXP B.V.
Inventor： Clemens Gerhardus Johannes de Haas , Johannes Petrus Antonius Frambach , Thomas John William Donaldson
IPC: G06F13/40
CPC classification number: G06F13/4027 , H03K19/0005 , H04L12/40032 , H04L25/0274 , H04L25/0278 , H04L2012/40215 , H04L2012/40273
Abstract: The present application relates to a circuit and a transceiver comprising the circuit. The circuit comprises two bus line terminals for coupling to a bus and a bridge circuit comprising two legs. Each leg comprises an adjustable pull resistance and an adjustable push resistance connected in series with a respective one of the two bus line terminals. The adjustable pull resistances and the adjustable push resistances of the bridge circuit enable to independently adjust a driver impedance and to independently adjust a differential driver voltage on the bus. The circuit may further comprise an edge detector is coupled to a transmit data input and configured to detect a transition on the transmit data input and to adjust the impedances of the adjustable pull resistances and the adjustable push resistances in response to the detected transition.
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公开(公告)号：US12224781B2
公开(公告)日：2025-02-11
申请号：US18463174
申请日：2023-09-07
Applicant: NXP B.V.
Inventor： Johannes Petrus Antonius Frambach , Cornelis Klaas Waardenburg , Stefan Paul van den Hoek , Gerard Arie de Wit
Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.
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公开(公告)号：US20230179454A1
公开(公告)日：2023-06-08
申请号：US18059595
申请日：2022-11-29
Applicant: NXP B.V.
Inventor： Cornelis Klaas Waardenburg , Johannes Petrus Antonius Frambach , Stefan Paul van den Hoek , Rinke de Jong
CPC classification number: H04L25/0276 , H03F3/45511 , H04L12/40 , H04L2012/40215
Abstract: An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.
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公开(公告)号：US20220247416A1
公开(公告)日：2022-08-04
申请号：US17647739
申请日：2022-01-12
Applicant: NXP B.V.
Abstract: The disclosure relates to a Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).
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公开(公告)号：US10594363B2
公开(公告)日：2020-03-17
申请号：US16206382
申请日：2018-11-30
Applicant: NXP B.V.
Inventor： Sujan Pandey , Johannes Petrus Antonius Frambach
Abstract: A transceiver, TX/RX PHY, arranged for bi-directional data communication of a node with a counterpart node connected to a point-to-point network using differential mode signaling over a single twisted-pair cable is disclosed. The transceiver, TX/RX PHY, includes a common mode choke arranged between of the TX/RX PHY and the single twisted-pair cable and provided for common mode current suppression. Further included is a switching arrangement arranged between the TX/RX PHY, the common mode choke and the single twisted-pair cable and configured to switchably change a polarity of one of the windings of the common mode choke. A detection section is included and coupled via the switching arrangement to the common mode choke and configured to detect a common mode signal on the single twisted-pair cable in response to a transmission of a test signal by the counterpart node.
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