公开(公告)号：US20150357456A1

公开(公告)日：2015-12-10

申请号：US14723247

申请日：2015-05-27

Applicant: NXP B.V.

Inventor： Godefridus Adrianus Maria HURKX ,  Jeroen Antoon CROON ,  Johannes Josephus Theodorus Marinus DONKERS ,  Stephan Bastiaan Simon HEIL ,  Jan SONSKY

IPC: H01L29/778 ,  H01L29/36 ,  H01L29/872 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/36 ,  H01L29/41766 ,  H01L29/66143 ,  H01L29/7786 ,  H01L29/872

Abstract: In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Abstract translation: 在示例性实施例中，异质结装置包括衬底，设置在衬底上的多层结构。 所述多层结构具有设置在所述基板顶部的具有第一半导体的第一层; 第二层具有第二半导体设置在第一层的顶部，限定它们之间的界面。 第二半导体与第一半导体不同，使得2D电子气体与界面相邻形成。 第一端子耦合到第一和第二层之间的界面的第一区域，并且第二端子耦合到第一层和第二层之间的界面的第二区域; 导电通道包括具有比第一层的另一区域更高的缺陷密度的第一层的金属或区域。 通道连接第二端子和第一层的区域，使得电荷在它们之间流动。

公开(公告)号：US20150325698A1

公开(公告)日：2015-11-12

申请号：US14704692

申请日：2015-05-05

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus DONKERS ,  Stephan Bastiaan Simon HEIL ,  Jan SONSKY

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L21/285 ,  H01L21/311 ,  H01L29/47 ,  H01L21/31

CPC classification number: H01L29/7839 ,  H01L21/28581 ,  H01L21/31 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/452 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: A semiconductor device comprising at least one active layer on a substrate and a first contact to the at least one active layer, the first contact comprising a metal in contact with the at least one active layer and a capping layer on the metal, the capping layer comprising a diffusion barrier, wherein the capping layer is patterned to form a pattern comprising regions of the contact covered by the capping layer and regions of the contact that are uncovered.

Abstract translation: 一种半导体器件，其包括在衬底上的至少一个有源层和与所述至少一个有源层的第一接触，所述第一接触包括与所述至少一个有源层接触的金属和所述金属上的覆盖层，所述覆盖层 包括扩散阻挡层，其中覆盖层被图案化以形成图案，该图案包括由覆盖层覆盖的接触区域和未被覆盖的接触区域。

公开(公告)号：US20140342527A1

公开(公告)日：2014-11-20

申请号：US14449522

申请日：2014-08-01

Applicant: NXP B.V.

Inventor： Peter Gerard STEENEKEN ,  Roel DAAMEN ,  Gerard KOOPS ,  Jan SONSKY ,  Evelyne GRIDELET ,  Coenraad Cornelis TAK

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76224 ,  H01L21/823878

Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.

公开(公告)号：US20140145208A1

公开(公告)日：2014-05-29

申请号：US14056648

申请日：2013-10-17

Applicant: NXP B.V.

Inventor： Matthias ROSE ,  Jan SONSKY ,  Philip RUTTER

IPC: H01L27/088 ,  H01L27/08

CPC classification number: H01L27/088 ,  H01L27/0814 ,  H03K17/567 ,  H03K17/6871 ,  H03K17/6874 ,  H03K17/74 ,  H03K2017/6875

Abstract: A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.

Abstract translation: 级联功率半导体电路在氮化镓或碳化硅FET的源极和栅极之间具有钳位电路，以提供共源共栅MOSFET晶体管的雪崩保护。