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公开(公告)号：US20220101934A1
公开(公告)日：2022-03-31
申请号：US17032913
申请日：2020-09-25
申请人： NXP USA, INC.
摘要： A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.
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公开(公告)号：US11170849B1
公开(公告)日：2021-11-09
申请号：US17024126
申请日：2020-09-17
申请人： NXP USA, INC.
摘要： A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.
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公开(公告)号：US11049539B1
公开(公告)日：2021-06-29
申请号：US16861562
申请日：2020-04-29
申请人： NXP USA, Inc.
摘要： A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.
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公开(公告)号：US11742012B2
公开(公告)日：2023-08-29
申请号：US17333109
申请日：2021-05-28
申请人： NXP USA, INC.
IPC分类号： G11C11/16 , G11C7/06 , G11C7/08 , G11C11/4074 , G11C13/00
CPC分类号： G11C11/1673 , G11C7/062 , G11C7/08 , G11C11/4074 , G11C2013/0042 , G11C2013/0045 , G11C2013/0054
摘要： A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.
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公开(公告)号：US11521692B2
公开(公告)日：2022-12-06
申请号：US17249906
申请日：2021-03-18
申请人： NXP USA, Inc.
发明人： Jon Scott Choy , Jacob T. Williams , Karthik Ramanan , Padmaraj Sanjeevarao , Maurits Mario Nicolaas Storms
摘要： A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuitry to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.
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公开(公告)号：US20220383925A1
公开(公告)日：2022-12-01
申请号：US17333109
申请日：2021-05-28
申请人： NXP USA, INC
IPC分类号： G11C11/16
摘要： A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.
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公开(公告)号：US20220301647A1
公开(公告)日：2022-09-22
申请号：US17249906
申请日：2021-03-18
申请人： NXP USA, Inc.
发明人： Jon Scott Choy , Jacob T. Williams , Karthik Ramanan , Padmaraj Sanjeevarao , Maurits Mario Nicolaas Storms
摘要： A memory includes a plurality of one-time programmable (OTP) memory cells, wherein each OTP memory cell includes a corresponding storage element capable of being in a permanently blown state or non-blown state. In the non-blown state, the corresponding storage element is capable of being in a low conductive state (LCS) or high conductive state (HCS). Control circuitry is configured to, in response to a received read request having a corresponding access address which selects a set of OTP memory cells, direct write circuitry to apply a voltage differential across the corresponding storage element of each selected OTP memory cell sufficient to set the corresponding storage element to a predetermined one of the LCS or HCS, and, after the write circuitry applies the voltage differential across the corresponding storage element, direct read circuity to read the selected OTP memory cells to output read data stored in the selected OTP memory cells.
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公开(公告)号：US11328784B2
公开(公告)日：2022-05-10
申请号：US17032913
申请日：2020-09-25
申请人： NXP USA, INC.
摘要： A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.
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公开(公告)号：US20220101903A1
公开(公告)日：2022-03-31
申请号：US17032537
申请日：2020-09-25
申请人： NXP USA, Inc.
IPC分类号： G11C11/16
摘要： A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.
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公开(公告)号：US11289144B1
公开(公告)日：2022-03-29
申请号：US17032537
申请日：2020-09-25
申请人： NXP USA, Inc.
IPC分类号： G11C11/16
摘要： A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.
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