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公开(公告)号：US20230410870A1
公开(公告)日：2023-12-21
申请号：US17807518
申请日：2022-06-17
申请人： NXP USA, Inc.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1673 , G11C11/1655 , G11C11/1657 , G11C11/1677
摘要： A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.
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公开(公告)号：US10916303B2
公开(公告)日：2021-02-09
申请号：US16410963
申请日：2019-05-13
申请人： NXP USA, Inc.
发明人： Anirban Roy , Yanzhe Tang
IPC分类号： G11C13/00
摘要： A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.
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公开(公告)号：US10699764B1
公开(公告)日：2020-06-30
申请号：US16220170
申请日：2018-12-14
申请人： NXP USA, INC.
发明人： Anirban Roy , Nihaar N. Mahatme
摘要： A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.
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公开(公告)号：US10573364B1
公开(公告)日：2020-02-25
申请号：US16219264
申请日：2018-12-13
申请人： NXP USA, Inc.
摘要： Embodiments of a magnetoresistive random access memory (MRAM) diagnostic system are provided, which includes: preconditioning all bit cells in an MRAM cell array to a data value of one during a diagnostic mode, wherein the MRAM cell array is implemented in an active side of a semiconductor substrate; applying a first magnetic disturb field having a predetermined field strength to the MRAM cell array, subsequent to the preconditioning, wherein the first magnetic disturb field is generated by an antenna implemented in a number of layers of conductive and dielectric material over the active side of the semiconductor substrate; performing a first error correcting code (ECC) read operation to read the MRAM cell array, subsequent to the applying the first magnetic disturb field; and in response to detecting at least one uncorrectable read during the first ECC read operation, setting a fail state and exiting the diagnostic mode.
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公开(公告)号：US10559356B2
公开(公告)日：2020-02-11
申请号：US15622738
申请日：2017-06-14
申请人： NXP USA, INC.
IPC分类号： G11C11/00 , G11C13/00 , G11C7/10 , G11C11/22 , G11C16/10 , G11C11/16 , G11C8/14 , G11C11/406
摘要： A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.
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公开(公告)号：US10403357B2
公开(公告)日：2019-09-03
申请号：US15707350
申请日：2017-09-18
申请人： NXP USA, INC.
发明人： Anirban Roy , Perry Pelley
摘要： An integrated circuit includes an array of resistive non-volatile memory cells having a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The integrated circuit includes a sense amplifier coupled to a first bit line of the plurality of bit lines and a corresponding first source line of the plurality of source lines. When a memory cell coupled to the first bit line is selected for a read operation, the sense amplifier is configured to, during a calibration phase of the read operation, store a first voltage representative of a leakage current on the first source line. The sense amplifier is also configured to, during a sense phase of the read operation, apply the stored first voltage to the first bit line and provide a first sense amplifier output indicative of a logic state of the selected memory cell.
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公开(公告)号：US20190179629A1
公开(公告)日：2019-06-13
申请号：US15839193
申请日：2017-12-12
申请人： NXP USA, Inc.
发明人： Anirban Roy , Anis M. Jarrar , Frank K. Baker, JR.
摘要： A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.
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公开(公告)号：US09922723B1
公开(公告)日：2018-03-20
申请号：US15407325
申请日：2017-01-17
申请人： NXP USA, Inc.
发明人： Anirban Roy
CPC分类号： G11C17/18 , G11C14/0081 , G11C17/02 , G11C17/16
摘要： A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.
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公开(公告)号：US20240321372A1
公开(公告)日：2024-09-26
申请号：US18188804
申请日：2023-03-23
申请人： NXP USA, Inc.
发明人： Anirban Roy , Nihaar N. Mahatme , Jon Scott Choy
摘要： A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.
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公开(公告)号：US20200211643A1
公开(公告)日：2020-07-02
申请号：US16410963
申请日：2019-05-13
申请人： NXP USA, Inc.
发明人： Anirban Roy , Yanzhe Tang
IPC分类号： G11C13/00
摘要： A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.
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