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    READ SOURCE LINE COMPENSATION IN A NON-VOLATILE MEMORY
    1.
    发明申请
    READ SOURCE LINE COMPENSATION IN A NON-VOLATILE MEMORY 有权
    在非易失性存储器中读取源线补偿

    公开(公告)号：US20060279996A1

    公开(公告)日：2006-12-14

    申请号：US11151168

    申请日：2005-06-10

    申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC分类号： G11C16/06

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

    摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

    摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

    Read source line compensation in a non-volatile memory
    2.
    发明授权
    Read source line compensation in a non-volatile memory 有权
    在非易失性存储器中读取源极线补偿

    公开(公告)号：US07180782B2

    公开(公告)日：2007-02-20

    申请号：US11151168

    申请日：2005-06-10

    申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC分类号： G11C16/28

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

    摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

    摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

    APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES
    7.
    发明申请
    APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES 有权
    用于检测存储器件中的字线泄漏的装置和方法

    公开(公告)号：US20090225607A1

    公开(公告)日：2009-09-10

    申请号：US12421523

    申请日：2009-04-09

    申请人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

    发明人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C29/02 ,  G11C8/08 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

    摘要： Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a power source or the second terminal. In an embodiment, the reference voltage is selected for identifying a leakage condition associated with the first word line. In another embodiment, the first switch is configured to couple the first word line to the power source for a first predetermined period of time to allow charging of the first word line. In another embodiment, the first switch is configured to couple the first word line to the second terminal of the comparator for at least a second predetermined period of time.

    摘要翻译： 本发明的一些实施例提供了一种存储器件，其包括具有第一字线的第一存储器阵列和具有耦合到参考电压的第一端子的比较器电路，以及耦合到选择性地将第一字线耦合到第一字线的第一开关的第二端子 电源或第二终端。 在一个实施例中，选择参考电压以识别与第一字线相关联的泄漏状况。 在另一个实施例中，第一开关被配置为将第一字线耦合到电源第一预定时间段以允许对第一字线充电。 在另一个实施例中，第一开关被配置为将第一字线耦合到比较器的第二端子至少第二预定时间段。

    Method and Apparatus for Repairing Memory
    9.
    发明申请
    Method and Apparatus for Repairing Memory 有权
    用于修复存储器的方法和装置

    公开(公告)号：US20080282107A1

    公开(公告)日：2008-11-13

    申请号：US11745244

    申请日：2007-05-07

    申请人： Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Su-Chueh Lo

    发明人： Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Su-Chueh Lo

    IPC分类号： G06F11/26

    CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C29/88

    摘要： Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.

    摘要翻译： 公开了一种方法和装置，其中诸如来自测试者的修复指令使得正在进行测试的集成电路用集成电路中的第二组存储器单元替换集成电路中的第一组存储器单元的缺陷位置， 尽管修复指令省略了集成电路的第一组存储单元的缺陷位置。

    Semiconductor device including memory cells and current limiter
    10.
    发明授权
    Semiconductor device including memory cells and current limiter 有权
    半导体器件包括存储单元和限流器

    公开(公告)号：US07355903B2

    公开(公告)日：2008-04-08

    申请号：US11181983

    申请日：2005-07-15

    申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

    发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

    IPC分类号： G11C7/10

    CPC分类号： G11C16/24

    摘要： A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.

    摘要翻译： 一种半导体器件，包括具有控制栅极，源极和漏极的存储单元; 以及耦合到源极的限流电路。 电流限制电路可以被配置为将漏极和源极之间的电流限制为不超过预定值; 响应于分别向控制栅极和漏极施加第一和第二电压而产生电流。 电流限制电路可以包括包括第一端子，第二端子和第三端子的晶体管，其中第一端子可以包括晶体管的源极，第三端子可以包括晶体管的漏极，并且第二端子可以 包括晶体管的栅极，并且其中可以将稳定的偏压施加到晶体管的第二端子。