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    READ SOURCE LINE COMPENSATION IN A NON-VOLATILE MEMORY
    1.
    发明申请
    READ SOURCE LINE COMPENSATION IN A NON-VOLATILE MEMORY 有权
    在非易失性存储器中读取源线补偿

    公开(公告)号：US20060279996A1

    公开(公告)日：2006-12-14

    申请号：US11151168

    申请日：2005-06-10

    申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC分类号： G11C16/06

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

    摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

    摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

    Read source line compensation in a non-volatile memory
    3.
    发明授权
    Read source line compensation in a non-volatile memory 有权
    在非易失性存储器中读取源极线补偿

    公开(公告)号：US07180782B2

    公开(公告)日：2007-02-20

    申请号：US11151168

    申请日：2005-06-10

    申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

    IPC分类号： G11C16/28

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

    摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

    摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

    Memory apparatus
    7.
    发明授权
    Memory apparatus 有权
    存储设备

    公开(公告)号：US08825978B2

    公开(公告)日：2014-09-02

    申请号：US13584393

    申请日：2012-08-13

    申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    IPC分类号： G06F12/00 ,  G06F13/42 ,  G11C29/00

    CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

    摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

    摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

    Memory device having a virtual ground array and methods using program algorithm to improve read margin loss
    8.
    发明授权
    Memory device having a virtual ground array and methods using program algorithm to improve read margin loss 有权
    具有虚拟接地阵列的存储器件和使用程序算法的方法来改善读取容差损失

    公开(公告)号：US07295471B2

    公开(公告)日：2007-11-13

    申请号：US11273120

    申请日：2005-11-14

    申请人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    发明人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0475 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459

    摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

    摘要翻译： 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

    MEMORY APPARATUS
    10.
    发明申请
    MEMORY APPARATUS 有权
    记忆装置

    公开(公告)号：US20130326184A1

    公开(公告)日：2013-12-05

    申请号：US13584393

    申请日：2012-08-13

    申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

    摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

    摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储器单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。