公开(公告)号：US5892604A

公开(公告)日：1999-04-06

申请号：US852396

申请日：1997-05-07

申请人： Naoaki Yamanaka ,  Kohei Shiomoto ,  Eiji Oki ,  Seisho Yasukawa

发明人： Naoaki Yamanaka ,  Kohei Shiomoto ,  Eiji Oki ,  Seisho Yasukawa

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04Q3/52 ,  H04Q11/00 ,  H04J14/02

CPC分类号： H04L12/5601 ,  H04L49/256 ,  H04Q11/0001 ,  H04L2012/5605 ,  H04L2012/5672

摘要： An ATM switch includes a plurality of input line corresponding units, a plurality of output line corresponding units, and a wavelength shifting unit. The wavelength shifting unit is arranged between the input line corresponding units and the output line corresponding units to shift optical signals having different wavelengths in a plurality of wavelength-multiplexed optical signals arriving from the input line corresponding units and output the wavelength-multiplexed optical signals. Each input line corresponding unit includes an input-side basic switch for distributing N (N is a positive integer) cells respectively input to input ports to N lines, an electro-optic converter for converting the cells into optical signals having different wavelengths in units of N lines, and a multiplexer for multiplexing the optical signals into one wavelength-multiplexed optical signal. Each output line corresponding unit includes a demultiplexer for demultiplexing the wavelength-multiplexed optical signal in units of wavelengths, an opto-electric converter for converting outputs from the demultiplexer into electrical signals, respectively, and an output-side basic switch for distributing the cells converted into the electrical signals to a plurality of output ports.

摘要翻译： ATM开关包括多个输入线对应单元，多个输出线对应单元和波长移位单元。 波长移位单元布置在输入线对应单元和输出线对应单元之间，以在从输入线对应单元到达的多个波长复用光信号中移位具有不同波长的光信号，并输出波长复用光信号。 每个输入线对应单元包括用于分配分别输入到N行的输入端口的N（N是正整数）单元的输入侧基本开关，用于将单元转换成具有不同波长的光信号的电光转换器，单元为 N线，以及用于将光信号复用为一个波分复用光信号的多路复用器。 每个输出线对应单元包括用于以波长为单位解复用波分复用光信号的解复用器，用于将从解复用器输出分别转换为电信号的光电转换器和用于分配转换的单元的输出侧基本开关 将电信号转换成多个输出端口。

公开(公告)号：US07292576B2

公开(公告)日：2007-11-06

申请号：US10972175

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US20050053067A1

公开(公告)日：2005-03-10

申请号：US10971524

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04Q11/04 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

公开(公告)号：US20050053096A1

公开(公告)日：2005-03-10

申请号：US10971676

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04Q11/04 ,  H04Q11/00

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US07339935B2

公开(公告)日：2008-03-04

申请号：US10971676

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US07136391B1

公开(公告)日：2006-11-14

申请号：US09376904

申请日：1999-08-18

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US07474664B2

公开(公告)日：2009-01-06

申请号：US10971524

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US20050083939A1

公开(公告)日：2005-04-21

申请号：US10972175

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nebeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nebeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04L12/933 ,  H04Q11/04 ,  H04Q11/00

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

公开(公告)号：US07652998B2

公开(公告)日：2010-01-26

申请号：US10731156

申请日：2003-12-10

申请人： Seisho Yasukawa ,  Koji Sugisono ,  Masanori Uga

发明人： Seisho Yasukawa ,  Koji Sugisono ,  Masanori Uga

IPC分类号： H04L1/00

CPC分类号： H04L45/48 ,  H04L12/1877 ,  H04L41/12 ,  H04L45/02 ,  H04L45/121 ,  H04L45/124 ,  H04L45/16

摘要： A multicast communication path calculation method is disclosed which includes the steps of: obtaining minimum delay paths from a source node to each destination node; selecting, as candidate nodes of a rendezvous point node, nodes on one of the obtained minimum delay paths; for each candidate node, calculating minimum delay paths from the candidate node to each destination node, and obtaining a difference between the maximum value and the minimum value among delays of the calculated minimum delay paths; selecting, as the rendezvous point node, a candidate node by which the difference is smallest; and outputting a minimum delay path from the source node to the rendezvous point node and minimum delay paths from the rendezvous point node to each destination node.

摘要翻译： 公开了一种组播通信路径计算方法，其包括以下步骤：获得从源节点到每个目的地节点的最小延迟路径; 作为会合点节点的候选节点选择所获得的最小延迟路径之一上的节点; 计算从所述候选节点到每个目的地节点的最小延迟路径，并且获得所计算的最小延迟路径的延迟中的最大值和最小值之间的差值; 选择作为会合点节点的差异最小的候选节点; 并输出从源节点到会合点节点的最小延迟路径和从会合点节点到每个目的地节点的最小延迟路径。

公开(公告)号：US07792099B2

公开(公告)日：2010-09-07

申请号：US12237912

申请日：2008-09-25

申请人： Seisho Yasukawa ,  Koji Sugisono ,  Masanori Uga

发明人： Seisho Yasukawa ,  Koji Sugisono ,  Masanori Uga

IPC分类号： H04L12/50 ,  H04Q11/00

CPC分类号： H04L45/48 ,  H04L45/12 ,  H04L45/121 ,  H04L45/16 ,  H04L45/50 ,  H04L45/70

摘要： A method of establishing a multicast transfer route is disclosed that can reduce the cost of entire route under a constraint on delay incurred between starting point and ending points. The method includes the steps of: computing the shortest route with respect to delay connecting the starting point and the plural ending points based on measurement result; computing delay from a node on the shortest route to each ending point and the greatest delay; removing, if the greatest delay satisfies a delay condition, the greatest-cost route from the shortest route in accordance with selection criteria effective for cost reduction; dividing the multicast transfer route into two route trees; and establishing separately computed route as a complementary route that complement the removed route for connecting the two route trees. A method of multicast label switching for realizing the above method is also disclosed. A multicast label switching route is established using hierarchical labels by establishing a common multicast label switching route using a first layer label and establishing plural partial multicast label switching routes for subgroup destinations using lower layer labels. A relay node recognizes the hierarchical labels thereby to label-switch using all hierarchical labels.

摘要翻译： 公开了一种建立多播传输路由的方法，可以在起始点和终点之间的延迟约束下降低整个路由的成本。 该方法包括以下步骤：基于测量结果计算相对于连接起始点和多个终点的延迟的最短路径; 计算从最短路径上的节点到每个终点的延迟和最大延迟; 如果最大延迟满足延迟条件，则根据有效降低成本的选择标准，从最短路由中删除最大成本路由; 将组播传输路由划分为两条路由树; 并建立单独计算的路由作为补充路由，用于补充用于连接两条路由树的已删除路由。 还公开了一种实现上述方法的组播标签交换方法。 使用分层标签建立组播标签交换路由，使用第一层标签建立公共组播标签交换路由，并使用下层标签为子组目的建立多个部分组播标签交换路由。 中继节点识别分层标签，从而使用所有分层标签进行标签交换。