公开(公告)号：US20130166731A1

公开(公告)日：2013-06-27

申请号：US13497636

申请日：2011-12-22

申请人： Naoaki Yamanaka ,  Eiji Oki ,  Yutaka Arakawa

发明人： Naoaki Yamanaka ,  Eiji Oki ,  Yutaka Arakawa

IPC分类号： H04W24/00

CPC分类号： H04W24/08 ,  H04L41/0893 ,  H04L41/5067 ,  H04L41/5096 ,  H04L43/0835 ,  H04L43/0858 ,  H04L43/087 ,  H04L43/0882 ,  H04L67/04 ,  H04L67/322 ,  H04W4/00 ,  H04W4/18 ,  H04W4/60 ,  H04W48/18

摘要： A method of notifying estimated QoEs (Quality of Experiences) for applications between a mobile terminal and a plurality of application servers that provide services of the applications, may measure first QoEs for the applications between the apparatus and the mobile terminal, measure second QoEs for the applications between the apparatus and the application server, estimate the estimated QoEs for the applications, based on the first and second QoEs for the applications, and notify the estimated QoEs to the mobile terminal.

公开(公告)号：US08134920B2

公开(公告)日：2012-03-13

申请号：US10546379

申请日：2004-02-20

申请人： Wataru Imajuku ,  Katsuhiro Shimano ,  Yoshihiro Takikawa ,  Eiji Oki ,  Yasutaka Okazaki

发明人： Wataru Imajuku ,  Katsuhiro Shimano ,  Yoshihiro Takikawa ,  Eiji Oki ,  Yasutaka Okazaki

IPC分类号： G01R31/08 ,  H04L12/28

CPC分类号： H04J14/0295 ,  H04J14/0284 ,  H04J14/0291 ,  H04L45/00 ,  H04L45/22 ,  H04Q11/0062 ,  H04Q2011/0073 ,  H04Q2011/0081 ,  H04Q2011/0088

摘要： In a disclosed backup path bandwidth keeping method for keeping bandwidth of a backup path to which an active path is switched when the active path becomes unavailable in nodes of a communication network, each node is connected to the same destination, and the method includes a backup path bandwidth keeping phase, for M (M is a natural number equal to or less than L) channels in L (L is a natural number) channels kept as backup path bandwidth, for notifying a destination-side node existing in a destination side of the backup path of identification number information of the M channels to be kept and identification information indicating that a path for which the bandwidth is to be kept is a backup path.

摘要翻译： 在公开的备用路径带宽保持方法中，当通信网络的节点中的活动路径变得不可用时，保持活动路径切换到的备用路径的带宽，每个节点连接到同一目的地，并且该方法包括备份 路径带宽保持阶段，对于保持作为备用路径带宽的L（L为自然数）的M（M为自然数等于或小于L）的信道，用于通知存在于目的地侧的目的地侧节点 要保留的M个信道的标识号信息的备份路径和指示要保持带宽的路径的标识信息是备份路径。

公开(公告)号：USRE43110E1

公开(公告)日：2012-01-17

申请号：US12072900

申请日：2008-02-28

申请人： Eiji Oki ,  Roberto Rojas-Cessa ,  Hung-Hsiang Jonathan Chao

发明人： Eiji Oki ,  Roberto Rojas-Cessa ,  Hung-Hsiang Jonathan Chao

IPC分类号： H04L12/28

CPC分类号： H04L49/1553 ,  H04L49/3045 ,  H04L49/3063 ,  H04L49/508 ,  H04L2012/5681

摘要： A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

摘要翻译： 用于输入缓冲交换机的基于流水线的最大尺寸匹配（PMM）调度方法利用最大匹配方案放松了用于仲裁的时序约束。 在PMM方法中，仲裁可以以流水线方式运行。 每个调度器被允许占用多于一个时隙进行匹配。 每个时隙，其中一个提供匹配的结果。 调度器可以采用预先存在的有效最大匹配算法，如iSLIP和DRRM。 PMM通过允许足够的时间进行多次迭代，最大限度地提高了所采用的仲裁方案的效率。 PMM在统一流量和公平性下保持100％吞吐量，以实现尽力而为的流量。

公开(公告)号：US20110016997A1

公开(公告)日：2011-01-27

申请号：US12935147

申请日：2009-03-30

申请人： Eiji Oki ,  Hidetoshi Kaida

发明人： Eiji Oki ,  Hidetoshi Kaida

IPC分类号： F16H19/04 ,  F16C29/02

CPC分类号： B62D3/12 ,  F16C29/02 ,  F16C33/201 ,  F16C35/02 ,  F16C43/02 ,  F16C2326/24 ,  F16H19/04 ,  Y10T74/18088 ,  Y10T74/216

摘要： A bush bearing 1 is comprised of: a synthetic resin-made bush 15 including a flexible semi-split cylindrical body 5 having an abutment portion 3 for slidably abutting against a rack shaft 25 and including a flexible open-ended annular body 14 which has a portion 6 formed integrally at one end face of the semi-split cylindrical body 5 and circular arc-shaped extended portions 12 and 13 whose distal ends 9 and 10 are opposed to each other with a clearance 11 in a circumferential direction R; and an elastic member 22 including an elastic body 21 for abutting against an outer surface 20 of the semi-split cylindrical body 5 and retained portions 16 and 17 which are respectively retained by both end portions 23 and 24.

摘要翻译： 衬套轴承1包括：合成树脂制衬套15，其包括柔性半分体圆柱体5，该柔性半分体圆柱体5具有用于可滑动地抵靠齿条轴25并具有柔性开口环形体14的抵接部3， 半圆柱体5的一个端面一体形成的部分6和其圆周方向R上的间隙11彼此相对的圆弧形延伸部分12和13; 以及包括弹性体21的弹性构件22，弹性体21用于抵靠半剖圆筒体5的外表面20和分别由两个端部23和24保持的保持部16和17。

公开(公告)号：US07339935B2

公开(公告)日：2008-03-04

申请号：US10971676

申请日：2004-10-22

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US07136391B1

公开(公告)日：2006-11-14

申请号：US09376904

申请日：1999-08-18

申请人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

发明人： Seisho Yasukawa ,  Naoki Takaya ,  Masayoshi Nabeshima ,  Eiji Oki ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1553 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/568 ,  H04L2012/5681 ,  H04Q11/0478

摘要： An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

摘要翻译： ATM开关包括第一级，第二级和第三级，其中每级包括至少一个基本开关，其中第一级，第二级和第三级被连接。 基本开关包括一部分，其指的是写入输入单元的标题中的时间信息，并以时间信息的升序将单元切换到输出端口。 另外，ATM交换机包括在第一级的基本交换机中的小区分配部分。 小区分配部分确定要转移的小区的路由，使得ATM交换机内的路由负载平衡。 ATM交换机还包括添加部分，其将到达时间信息添加到到达的小区作为时间信息。

公开(公告)号：US07103056B2

公开(公告)日：2006-09-05

申请号：US09872892

申请日：2001-06-01

申请人： Hung-Hsiang Jonathan Chao ,  Eiji Oki

发明人： Hung-Hsiang Jonathan Chao ,  Eiji Oki

IPC分类号： H04L12/28 ,  H04L12/54 ,  H04Q11/00

CPC分类号： H04L49/1515 ,  H04L49/1569

摘要： A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided. A hierarchical arbitration scheme used in the input modules reduces the time needed for scheduling and reduces connection lines.

公开(公告)号：US20060018313A1

公开(公告)日：2006-01-26

申请号：US10533397

申请日：2004-03-24

申请人： Eiji Oki ,  Daisaku Shimazaki ,  Kohei Shiomoto ,  Naoaki Yamanaka

发明人： Eiji Oki ,  Daisaku Shimazaki ,  Kohei Shiomoto ,  Naoaki Yamanaka

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/50 ,  H04Q2011/0077

摘要： A network is realized having GMPLS and IP/MPLS mixed, in which an IP/MPLS node can be operated as is without replacing the IP/MPLS node with a node having a GMPLS function, even if the GMPLS and IP/MPLS are mixed. To match with the protocol of the IP/MPLS node outside of a GMPLS cloud, the GMPLS+IP/MPLS node (edge) establishes a PSC-LSP between GMPLS+IP/MPLS nodes (edge), uses the PSC-LSP as an IP/MPLS link from the viewpoint of the IP/MPLS node, and operates signaling of an MPLS-LSP establishment requested from the IP/MPLS.

摘要翻译： 实现了具有GMPLS和IP / MPLS混合的网络，其中IP / MPLS节点可以被操作，而不用具有GMPLS功能的节点替换IP / MPLS节点，即使混合了GMPLS和IP / MPLS。 为了与GMPLS云以外的IP / MPLS节点的协议相匹配，GMPLS + IP / MPLS节点（边缘）在GMPLS + IP / MPLS节点（边缘）之间建立PSC-LSP，使用PSC-LSP作为 从IP / MPLS节点的角度来看IP / MPLS链路，并且操作从IP / MPLS请求的MPLS-LSP建立信令。

公开(公告)号：US5953341A

公开(公告)日：1999-09-14

申请号：US936667

申请日：1997-09-24

申请人： Naoaki Yamanaka ,  Eiji Oki ,  Tomoaki Kawamura ,  Tsuneo Matsumura

发明人： Naoaki Yamanaka ,  Eiji Oki ,  Tomoaki Kawamura ,  Tsuneo Matsumura

IPC分类号： H04L12/54 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5647 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5679

摘要： A contention control circuit which temporarily stores cells arriving from a respective plurality of input lines to output cells to a single output line without collisions. The contention control circuit compares, at each input line in turn, the priority of the cell that has arrived from that input line, with the priority of the cell selected from among the cells that have arrived from preceding input lines as the cell having the highest priority, and again selects the cell with the higher priority.

摘要翻译： 一种竞争控制电路，临时存储从相应的多个输入线到达的信元，以将单元输出到单个输出线而没有冲突。 竞争控制电路在每个输入线依次比较从该输入线路到达的小区的优先级，从从先前输入线路到达的小区中选择的小区的优先级比较为具有最高的小区 优先级，再次选择优先级更高的单元。

公开(公告)号：US08081881B2

公开(公告)日：2011-12-20

申请号：US12417173

申请日：2009-04-02

申请人： Eiji Oki ,  Akira Misawa ,  Masaru Katayama ,  Satoru Okamoto

发明人： Eiji Oki ,  Akira Misawa ,  Masaru Katayama ,  Satoru Okamoto

IPC分类号： H04B10/00 ,  H04B10/02 ,  H04B10/08 ,  H04B10/20

CPC分类号： H04J14/0284 ,  H04B10/299 ,  H04J14/0227 ,  H04J14/0246 ,  H04J14/025 ,  H04J14/0256 ,  H04J14/0257 ,  H04J14/0258 ,  H04J14/0267 ,  H04J14/0269 ,  H04L41/12

摘要： An economical optical network is constituted by effectively using network resources by using the minimum number of, or minimum capacity of 3R repeaters. 3R section information corresponding to topology information on the optical network to which an optical node device itself belongs is stored, and the 3R section information stored is referred so as to autonomously determine whether or not the optical node device itself is an optical node device for implementing the 3R relay when setting an optical path passing through the optical node device itself. Alternatively, when the optical node device itself is a source node, another optical node device for implementing the 3R relay among the other optical node devices through which the optical path from the optical node device itself to the destination node passes is identified, and this identified optical node device is requested to implement the 3R relay when setting an optical path in which the optical node device itself is a source node.

摘要翻译： 通过使用3R中继器的最小或最小容量有效地使用网络资源来构成经济的光网络。 存储与光节点设备本身所属的光网络上的拓扑信息对应的3R部分信息，并且参考存储的3R部分信息，以便自主地确定光节点设备本身是否是用于实现的光节点设备 当设置通过光节点设备本身的光路时，3R继电器。 或者，当光节点设备本身是源节点时，识别用于在从光节点设备本身到目的地节点通过的光路经过的其他光节点设备中实现3R中继器的另一光节点设备，并且这被识别 要求光节点设备在设置光节点设备本身是源节点的光路时实现3R中继。