公开(公告)号：US20120054416A1

公开(公告)日：2012-03-01

申请号：US13050431

申请日：2011-03-17

申请人： Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Naoki KOBAYASHI ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G06F12/02

CPC分类号： G11C11/5628

摘要： According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y

摘要翻译： 根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。 存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序 到记忆体细胞。 控制器包括基于x位产生y位（y为整数和y

公开(公告)号：US08605500B2

公开(公告)日：2013-12-10

申请号：US13050431

申请日：2011-03-17

申请人： Naoki Kobayashi ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Naoki Kobayashi ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C11/34

CPC分类号： G11C11/5628

摘要： According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y

摘要翻译： 根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。 存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序 到记忆体细胞。 控制器包括基于x位产生y位（y为整数和y

公开(公告)号：US07505315B2

公开(公告)日：2009-03-17

申请号：US11850252

申请日：2007-09-05

申请人： Mitsuaki Honma ,  Noboru Shibata

发明人： Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483

摘要： A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2x threshold voltages, the x-bit information being able to be read from each memory cell by applying a read voltage to the corresponding word line; a row decoder connected to the word lines to supply voltages to the word lines to operate the memory cells; and a sense amplifier device connected to the bit lines to read data stored in the memory cells and to hold the read data and data written to the memory cells, wherein the x-bit information corresponding to a certain threshold voltage differs from that corresponding to the adjacent threshold voltage by only 1 bit, 2x−1 of the read voltages are each set for a pair of adjacent threshold voltages, and applying any of the read voltages to the word line determines the x-bit information stored in the memory cell, and at least two read voltages are set in order to determine information for each of the x bits.

摘要翻译： 非易失性半导体存储装置包括具有连接到字线和位线的多个存储单元的存储单元阵列，并且其中存储x（x是等于或大于3的整数）位的不同信息 与2x个阈值电压相关联，通过向对应的字线施加读取电压，能够从每个存储单元读取x位信息; 连接到字线的行解码器以向字线提供电压以操作存储器单元; 以及连接到位线的读出放大器装置，以读取存储在存储单元中的数据，并将写入的数据和数据保存在存储单元中，其中对应于一定阈值电压的x位信息不同于与 相邻的阈值电压仅为1位，读取电压的2x-1分别针对一对相邻阈值电压设定，并且将任何读取电压施加到字线确定存储在存储器单元中的x位信息，以及 设置至少两个读取电压以便确定每个x位的信息。

公开(公告)号：US07349249B2

公开(公告)日：2008-03-25

申请号：US11389083

申请日：2006-03-27

申请人： Mitsuaki Honma ,  Noboru Shibata ,  Kazunori Kanebako

发明人： Mitsuaki Honma ,  Noboru Shibata ,  Kazunori Kanebako

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5646

摘要： A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.

摘要翻译： 半导体存储器件包括其中布置有存储器单元的存储单元阵列，每个存储器单元存储由其阈值电压定义的数据，其中存储单元阵列包括第一和第二区域; 第一区域存储用多个写入步骤写入的多值数据; 并且第二区域存储由第一和第二逻辑状态定义的二进制数据，其阈值级别通过适于多值数据写入的多个写入步骤来控制。

公开(公告)号：US20110205805A1

公开(公告)日：2011-08-25

申请号：US12672335

申请日：2008-09-02

申请人： Mitsuaki Honma ,  Noboru Shibata

发明人： Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5646

摘要： A semiconductor memory device executes a writing operation based on a first bit assignment pattern at the time of writing. The first bit assignment pattern is created such that pieces of x-bit data assigned to adjacent threshold distributions have only a one-bit difference therebetween and an alignment of data on the same digit of 2x pieces of x-bit data corresponding to an alignment of 2x pieces of threshold distributions contains at least two transition points of “0” and “1”. The semiconductor memory device operates at the time of reading such that a read voltage corresponding to the transition points of “0” and “1” is applied to the word line on a page basis to determine x-bit data stored in the memory cell one-bit by one-bit based on the first assignment pattern. The page contains a set of data on the same digit bit in pieces of x-bit data stored in the memory cells connected to the word line.

摘要翻译： 半导体存储器件在写入时基于第一位分配模式执行写入操作。 第一位分配模式被创建，使得分配给相邻阈值分布的X位数据片段之间只有一位差异，并且对应于与x位数据对齐的2个x位数据的相同数位上的数据对齐 2个阈值分布包含至少两个转换点“0”和“1”。 半导体存储器件在读取时操作，使得对应于“0”和“1”的转换点的读取电压在页面上施加到字线，以确定存储在存储器单元中的x位数据 - 基于第一个分配模式位1比特。 该页面包含存储在连接到字线的存储单元中的x位数据的相同位数位上的一组数据。

公开(公告)号：US20100124109A1

公开(公告)日：2010-05-20

申请号：US12562439

申请日：2009-09-18

申请人： Mitsuaki HONMA ,  Noboru Shibata

发明人： Mitsuaki HONMA ,  Noboru Shibata

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5646

摘要： A memory cell array is configured so that a plurality of memory cells which are connected to a word line and a bit line store one value out of n values (n is a natural number of 2 or more) in one memory cell and are arranged in a matrix. A control circuit controls electronic potentials of the word line and the bit line in response to input data to write data in the memory cells. When writing data in the first memory cell of the memory cell array, the control circuit varies a writing level on the basis of writing data to write in a second memory cell adjacent to the first memory cell.

摘要翻译： 存储单元阵列被配置为使得连接到字线和位线的多个存储单元存储在一个存储单元中的n个值（n是2或更多的自然数）中的一个值，并且被布置在 一个矩阵。 控制电路响应于输入数据来控制字线和位线的电位，以将数据写入存储单元。 当在存储单元阵列的第一存储单元中写入数据时，控制电路基于写入数据而改变写入电平以写入与第一存储单元相邻的第二存储单元。

公开(公告)号：US20060227602A1

公开(公告)日：2006-10-12

申请号：US11352363

申请日：2006-02-13

申请人： Mitsuaki Honma ,  Noboru Shibata

发明人： Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5641

摘要： A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from the memory cell array and externally supplied expectance data in the sense amplifier circuit.

公开(公告)号：US20120182800A1

公开(公告)日：2012-07-19

申请号：US13434951

申请日：2012-03-30

申请人： Mitsuaki HONMA ,  Noboru Shibata

发明人： Mitsuaki HONMA ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/06

摘要： A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels.

摘要翻译： 存储单元阵列连接到字线和位线，并且被配置为使得在一个存储单元中存储n个电平（n是大于4的自然数）的一个电平的多个存储单元被排列成矩阵。 控制电路根据输入数据控制字线和位线的电位，并将数据写入存储单元。 控制电路将对应于写入数据的写入电压施加到存储单元。 每个写入数据的写入电压不同。 在写入电压施加操作相对于所有n个电平结束之后，对每个写入数据执行验证操作。

公开(公告)号：US07872910B2

公开(公告)日：2011-01-18

申请号：US12397369

申请日：2009-03-04

申请人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

发明人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C2211/5646

摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

摘要翻译： 在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。 位线控制电路连接到位线以控制位线。 字线控制电路将多位数据读取电压作为字线电压施加到字线。 多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。 此外，它将软值读取电压作为字线电压施加到字线。 软值读取电压小于阈值电压分布的上限并且大于其下限。 似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

公开(公告)号：US07808821B2

公开(公告)日：2010-10-05

申请号：US12204207

申请日：2008-09-04

申请人： Mikio Ogawa ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

发明人： Mikio Ogawa ,  Katsuaki Isobe ,  Yoshikazu Takeyama ,  Mitsuaki Honma ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621

摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.

摘要翻译： 写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。 对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。 无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。 在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。