公开(公告)号：US20070168809A1

公开(公告)日：2007-07-19

申请号：US11199972

申请日：2005-08-09

申请人： Naoki Kiryu ,  Nathan Chelstrom ,  Mack Riley ,  Louis Bushard

发明人： Naoki Kiryu ,  Nathan Chelstrom ,  Mack Riley ,  Louis Bushard

IPC分类号： G01R31/28

CPC分类号： G01R31/3187 ,  G01R31/31724 ,  G01R31/318563

摘要： Systems and methods for performing logic built-in self-tests (LBISTs) in which an LBIST controller provides control signals to multiple LBIST satellites that are co-located with different functional blocks of the device under test, such as processor cores in a multiprocessor integrated circuit. Because the data paths for each satellite are shorter than data paths in conventional LBIST architectures, fewer latches are needed to synchronize the delivery of data to scan chains in the satellites. In one embodiment, each satellite includes a pseudorandom bit pattern generator (PRPG,) scan chains and a multiple-input signature register (MISR). In one embodiment, the LBIST circuitry also includes a control scan chain that is coupled to each of the LBIST satellites and configured to scan data into and out of the LBIST satellites.

摘要翻译： 用于执行逻辑内置自检（LBIST）的系统和方法，其中LBIST控制器向与被测器件的不同功能块共同定位的多个LBIST卫星提供控制信号，例如多处理器集成中的处理器核 电路。 由于每个卫星的数据路径比常规LBIST架构中的数据路径短，因此需要较少的锁存器来同步数据传输到卫星中的扫描链。 在一个实施例中，每个卫星包括伪随机位模式生成器（PRPG），扫描链和多输入签名寄存器（MISR）。 在一个实施例中，LBIST电路还包括控制扫描链，其耦合到每个LBIST卫星并被配置为扫描数据进入和离开LBIST卫星。

公开(公告)号：US20070234159A1

公开(公告)日：2007-10-04

申请号：US11278313

申请日：2006-03-31

申请人： LOUIS BUSHARD ,  Nathan Chelstrom ,  Naoki Kiryu ,  David Krolak

发明人： LOUIS BUSHARD ,  Nathan Chelstrom ,  Naoki Kiryu ,  David Krolak

IPC分类号： G01R31/28

CPC分类号： G01R31/318525 ,  G01R31/3187

摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

摘要翻译： 一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。 逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。 响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。 响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。 执行非扫描锁存器环中的逻辑路径。 非扫描锁存器是逻辑路径的一部分。 从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

公开(公告)号：US20070130489A1

公开(公告)日：2007-06-07

申请号：US11295057

申请日：2005-12-06

申请人： Naoki Kiryu ,  Mack Riley ,  Nathan Chelstrom

发明人： Naoki Kiryu ,  Mack Riley ,  Nathan Chelstrom

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed to determine whether any of the processor cores is malfunctioning. If none of the processor cores malfunctions, the processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor is fully functional. If one or more processor cores malfunctions, these processor cores are isolated and the remaining processor cores are tested in conjunction with the supporting functional blocks of the device to determine whether the multiprocessor operates properly with reduced functionality.

摘要翻译： 用于在数字电路中执行逻辑内置自检（LBIST）的系统和方法，其中电路功能块中的边界扫描链可以选择性耦合/去耦以在LBIST测试期间隔离功能块。 在一个实施例中，多处理器芯片的处理器核是隔离的，并且执行LBIST测试以确定任何处理器核心是否发生故障。 如果没有处理器内核发生故障，处理器内核将与设备的支持功能块一起进行测试，以确定多处理器是否完全正常工作。 如果一个或多个处理器内核发生故障，则这些处理器内核是隔离的，剩余的处理器内核将与设备的支持功能块一起进行测试，以确定多处理器是否以降低的功能正常运行。

公开(公告)号：US20050138509A1

公开(公告)日：2005-06-23

申请号：US10744917

申请日：2003-12-23

申请人： Naoki Kiryu ,  Louis Bushard

发明人： Naoki Kiryu ,  Louis Bushard

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04 ,  H03K3/84 ,  H03K19/00

CPC分类号： G01R31/318536 ,  G01R31/318385 ,  G01R31/318566

摘要： Systems and methods for improved performance of built-in-self-tests (BISTs) in integrated circuits, where variability is introduced into the self tests to improve the coverage of the tests. In one embodiment, an LBIST system includes scan chains interposed between levels of functional logic in a circuit under test. An exemplary method includes the steps of, for each of one or more initial scan chains, filling the initial scan chains with data comprising a pseudorandom pattern of bits, determining a number of levels of functional circuitry and corresponding subsequent scan chains through which to propagate the data and propagating the data from the initial scan chains through the determined number of levels of functional circuitry and corresponding subsequent scan chains. The number of levels of circuitry through which data is propagated is varied from one test cycle to another based upon a pseudorandom input signal.

摘要翻译： 集成电路中内置自检（BIST）的性能改进的系统和方法，其中可变性被引入到自我测试中以提高测试的覆盖范围。 在一个实施例中，LBIST系统包括插入在被测电路中的功能逻辑电平之间的扫描链。 一个示例性方法包括以下步骤：对于一个或多个初始扫描链中的每一个，用包括位的伪随机模式的数据填充初始扫描链，确定功能电路的数量级和相应的后续扫描链，通过该扫描链传播 数据，并通过确定数量的功能电路和对应的后续扫描链的数量从初始扫描链传播数据。 基于伪随机输入信号，数据传播的电路的数量从一个测试周期变化到另一个。

公开(公告)号：US07478304B2

公开(公告)日：2009-01-13

申请号：US11936921

申请日：2007-11-08

申请人： Tilman Gloekler ,  Christian Habermann ,  Naoki Kiryu ,  Joachim Kneisel ,  Johannes Koesters

发明人： Tilman Gloekler ,  Christian Habermann ,  Naoki Kiryu ,  Joachim Kneisel ,  Johannes Koesters

IPC分类号： G01R31/28

CPC分类号： G06F17/5022 ,  G01R31/318357

摘要： The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

摘要翻译： 本发明提供一种用于对TTP-LBIST应用外部时钟和数据模式的装置和计算机程序产品。 在仿真器中设置了被测逻辑的仿真模型。 接下来，用户设置外部LBIST块，其包括预先验证的内部时钟和数据模式逻辑，并将该块连接到仿真模型中的逻辑。 内部时钟和数据模式逻辑提供了用于LBIST的OPCG模式的输入模式。 该内部时钟和数据模式逻辑已经通过设计工作进行了验证。 因此，内部模式发生器成为模拟模型中的外部模式发生器。 外部LBIST块应用外部时钟和数据模式，随后用户接收并处理这些输出模式以确定逻辑是否正常工作。

公开(公告)号：US07308634B2

公开(公告)日：2007-12-11

申请号：US11096787

申请日：2005-04-01

申请人： Naoki Kiryu

发明人： Naoki Kiryu

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G01R31/318536

摘要： Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between portions of the functional logic. Pseudorandom bit patterns are scanned into the scan chains so that they can be propagated through the functional logic following the scan chains. The resulting bit patterns are captured in scan chains following the functional logic and then scanned out of these scan chains. An LBIST controller causes functional operations in different portions of the functional logic to be performed at different times during a functional phase of a test cycle. The functional operations may be performed at a normal operating speed, while scan shift operations may be performed at a lower speed.

摘要翻译： 用于在数字电路中执行逻辑内置自检（LBIST）的系统和方法，其中LBIST电路被配置为在不同时间通过电路的功能逻辑的不同部分传播数据。 在一个实施例中，逻辑电路包括LBIST组件，其包括置于功能逻辑部分之间的一组扫描链。 伪随机位模式被扫描到扫描链中，使得它们可以通过跟随扫描链的功能逻辑传播。 产生的位模式在功能逻辑之后的扫描链中捕获，然后从这些扫描链中扫描出来。 LBIST控制器使功能逻辑的不同部分的功能操作在测试周期的功能阶段的不同时间执行。 可以以正常操作速度执行功能操作，而可以以较低速度执行扫描移位操作。

公开(公告)号：US20070011537A1

公开(公告)日：2007-01-11

申请号：US11158601

申请日：2005-06-22

申请人： Naoki Kiryu

发明人： Naoki Kiryu

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits. In one embodiment, a system has first and second target logic, each of which has LBIST circuitry incorporated therein. The system also includes comparison circuitry which is coupled to the first and second LBIST circuitry. The comparison circuitry is configured to detect differences between data generated by the LBIST circuitry of the first target logic and data generated by the LBIST circuitry of the second target logic (e.g., MISR signature values.) The comparison circuitry is also configured to provide information localizing the sources of the differences. In one embodiment, this localizing information comprises values from a test cycle counter, a scan shift counter and a set of XOR gates that compare the bits of the MISR values.

摘要翻译： 用于在数字电路中执行逻辑内置自检（LBIST）的系统和方法。 在一个实施例中，系统具有第一和第二目标逻辑，每个目标逻辑具有并入其中的LBIST电路。 该系统还包括耦合到第一和第二LBIST电路的比较电路。 比较电路被配置为检测由第一目标逻辑的LBIST电路产生的数据与由第二目标逻辑的LBIST电路产生的数据之间的差异（例如，MISR签名值）。比较电路还被配置为提供信息定位 差异的根源。 在一个实施例中，该定位信息包括来自测试周期计数器，扫描移位计数器和一组比较MISR值的XOR门的值。

公开(公告)号：US20060174178A1

公开(公告)日：2006-08-03

申请号：US11049522

申请日：2005-02-02

申请人： Naoki Kiryu

发明人： Naoki Kiryu

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318552

摘要： Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate that is reduced in one or more steps from a first rate that is used in a functional phase of LBIST testing to a reduced rate that is used in a scan shift phase. The effective clock rate is stepped back up at the end of the scan shift phase to the first rate which is used in the following functional phase.

摘要翻译： 在数字电路中执行逻辑内置自检（LBIST）的系统和方法，其中LBIST电路的扫描移位操作以降低的速率进行。 在一个实施例中，在提供给LBIST电路之前门控基本时钟信号。 时钟信号被选通以产生从LBIST测试的功能阶段中使用的第一速率到在扫描移位阶段中使用的降低速率的一个或多个步骤中减少的有效时钟速率。 在扫描移位阶段结束时，有效时钟速率被逐步恢复到在以下功能阶段中使用的第一速率。

公开(公告)号：US07080298B2

公开(公告)日：2006-07-18

申请号：US10358461

申请日：2003-02-04

申请人： Naoki Kiryu ,  Louis B Bushard

发明人： Naoki Kiryu ,  Louis B Bushard

IPC分类号： G01R31/28

CPC分类号： G01R31/318566 ,  G01R31/318385 ,  G01R31/318547

摘要： A method for testing an electronic circuit includes selecting an input signal using a first multiplexer, selecting a signal to be input to the first multiplexer using at least one other multiplexer, and controlling the at least one other multiplexer using a selection signal output from a control circuit.

摘要翻译： 一种用于测试电子电路的方法包括使用第一多路复用器选择输入信号，使用至少一个其他多路复用器选择要输入到第一多路复用器的信号，以及使用从控制器输出的选择信号来控制至少一个其他复用器 电路。

公开(公告)号：US08130570B2

公开(公告)日：2012-03-06

申请号：US12888682

申请日：2010-09-23

申请人： Akihiko Fukui ,  Naoki Kiryu

发明人： Akihiko Fukui ,  Naoki Kiryu

IPC分类号： G11C7/10

CPC分类号： G11C29/14 ,  G01R31/318541 ,  G01R31/318594 ,  G11C29/023 ,  G11C29/12015 ,  G11C2029/3202

摘要： A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock.

摘要翻译： 数据传输电路包括：异步存储器，用第一时钟从第一时钟域写入传输数据，并且用第二时钟将写入的传输数据从其读取到第二时钟域; 扫描触发器，其输入端子连接到位于数据路径上的传输数据的第一位置，从异步存储器连接到第二时钟域，并且其输出端子连接到位于数据路径上的第二位置 的传输数据，从异步存储器到第一位置; 以及时钟选择器，其从第一时钟和第二时钟选择时钟来驱动扫描触发器。