摘要:
A power circuit includes a coil that charges an electric charge of an input voltage, a switch device that controls charging and discharging of the coil, a diode that rectifies the flow of the electric charge from the coil, a capacitor that stabilizes an output voltage when the switch device is turned on, and a driving circuit that controls ON and OFF states of the switch device. The power circuit alternately switches the ON and OFF states of the switch device to control charging and discharging of the coil and the capacitor, and generates and supplies an output voltage higher than the input voltage, and the driving circuit controls the off-period of the switch device according to the on-period of the switch device and the voltage ratio of the output voltage and the input voltage while changing the repetition period of the ON and OFF states of the switch device.
摘要:
Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.
摘要:
Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.
摘要:
A liquid crystal display is provided with: a tap adjustment register for adjusting a gray scale level to a gray scale voltage in intermediate portions close to the end portions of the gamma characteristic; and a partial-voltage-ratio adjustment register for adjusting a ratio of a gray scale voltage among a plurality of gray scale levels in the intermediate portions close to the end portions of the gamma characteristic, in addition to an amplitude adjustment register for adjusting an amplitude of a gamma characteristic which determines a relation between gray scale levels and gray scale voltages or brightness levels on a display panel; a gradient adjustment register for adjusting a gradient of intermediate portions of the gamma characteristic while fixing end portions of the gamma characteristic; and a fine adjustment register for finely adjusting the intermediate portions of the gamma characteristic for each gray scale level.
摘要:
A liquid crystal display is provided with: a tap adjustment register for adjusting a gray scale level to a gray scale voltage in intermediate portions close to the end portions of the gamma characteristic; and a partial-voltage-ratio adjustment register for adjusting a ratio of a gray scale voltage among a plurality of gray scale levels in the intermediate portions close to the end portions of the gamma characteristic, in addition to an amplitude adjustment register for adjusting an amplitude of a gamma characteristic which determines a relation between gray scale levels and gray scale voltages or brightness levels on a display panel; a gradient adjustment register for adjusting a gradient of intermediate portions of the gamma characteristic while fixing end portions of the gamma characteristic; and a fine adjustment register for finely adjusting the intermediate portions of the gamma characteristic for each gray scale level.
摘要:
In a display driver, a period D following a period P in one scanning period is divided into periods R, G, and B in which data voltages are applied to data lines R, G, and B, and two output orders of the data voltage such as the period R→the period G→period B and the period B→the period G→period R are switched in each two frames.
摘要:
A driving circuit provided by the present invention is characterized in that the driving circuit selects a gray-scale voltage in accordance with high-order bits of display data from a group of gray-scale voltages with their voltage level varying step by step from fractional time period to fractional time period, which are set in advance, and outputs the selected gray-scale voltage during a time period between the start of a scanning period and a time at which a number assigned to a fractional time period matches quantitative information contained in low-order bits of the display data. In addition, the driving circuit provided by the present invention is also characterized in that the time ratio of the first fractional time period is set at a relatively high value while the time ratios of the second and subsequent fractional time periods are each set at a relatively low value.
摘要:
A driver for driving a display device, which has signal lines arranged in a first direction, scanning lines arranged in a second direction intersecting with the first direction, and pixels provided to correspond to intersections of the signal lines and the scanning lines, each pixel having a pixel electrode connected to the signal line through a capacitance and a switching element whose first, second, and third terminals are connected respectively to the signal line, the scanning line, and the pixel electrode, comprises: a converter for converting inputted display data to a gray-scale voltage and outputting the gray-scale voltage to the signal lines; and a switching circuit for opening/closing a first electrical coupling provided between the signal line and the converter and a second electrical coupling provided between the signal lines, wherein one scanning period for scanning the scanning lines includes a first period during which the switching circuit closes the first electrical coupling and opens the second electrical coupling, and a second period during which the switching circuit opens the first electrical coupling and closes the second electrical coupling.
摘要:
In consideration of the current leakage path of a liquid crystal panel and a signal line voltage fluctuation due to the current leakage path, a γ adjusting function (second driving method) is applied for each divided period in the first driving method. In a signal line driving unit, a gray scale voltage obtained by adding or subtracting a voltage fluctuation value different in each of the output periods of each gray scale is generated, and a gray scale voltage taking the voltage fluctuation value into consideration is applied to a signal line.
摘要:
A driving circuit provided by the present invention is characterized in that the driving circuit selects a gray-scale voltage in accordance with high-order bits of display data from a group of gray-scale voltages with their voltage level varying step by step from fractional time period to fractional time period, which are set in advance, and outputs the selected gray-scale voltage during a time period between the start of a scanning period and a time at which a number assigned to a fractional time period matches quantitative information contained in low-order bits of the display data. In addition, the driving circuit provided by the present invention is also characterized in that the time ratio of the first fractional time period is set at a relatively high value while the time ratios of the second and subsequent fractional time periods are each set at a relatively low value.