公开(公告)号：US06411144B1

公开(公告)日：2002-06-25

申请号：US09633263

申请日：2000-08-04

申请人： Narito Matsuno

发明人： Narito Matsuno

IPC分类号： H03L706

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/105 ,  Y10S331/02

摘要： An effective range for a control voltage to operate a VCO is set in order to prevent the VCO from operating in the reverse characteristic area. A monitoring circuit is provided for monitoring the control voltage. When the control voltage is out of the effective range, the monitoring circuit outputs a monitor signal and inputs it into a charge pump. When the charge pump receives the monitor signal it generates a fixed voltage. Thus, when the reference signal is not inputted, the control voltage is maintained within a prespecified voltage range and the VCO oscillates within a prespecified frequency range.

摘要翻译： 设置用于操作VCO的控制电压的有效范围，以防止VCO在反向特征区域中操作。 提供监控电路用于监视控制电压。 当控制电压超出有效范围时，监控电路输出监控信号并将其输入电荷泵。 当电荷泵接收到监视信号时，它产生固定电压。 因此，当不输入参考信号时，控制电压保持在预定的电压范围内，并且VCO在预先指定的频率范围内振荡。

公开(公告)号：US06639441B2

公开(公告)日：2003-10-28

申请号：US10046186

申请日：2002-01-16

申请人： Masaaki Ono ,  Masataka Kazuno ,  Narito Matsuno

发明人： Masaaki Ono ,  Masataka Kazuno ,  Narito Matsuno

IPC分类号： H03K3017

CPC分类号： H03K5/1534 ,  H03K5/133 ,  H03K5/1565 ,  H03K5/159

摘要： A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.

公开(公告)号：US08548401B2

公开(公告)日：2013-10-01

申请号：US13324544

申请日：2011-12-13

申请人： Akio Sasaki ,  Setsuya Nagaya ,  Narito Matsuno ,  Kenji Iwai

发明人： Akio Sasaki ,  Setsuya Nagaya ,  Narito Matsuno ,  Kenji Iwai

IPC分类号： H04B1/04

CPC分类号： H03F3/24 ,  H03F1/0233 ,  H03F3/189 ,  H03F2200/105 ,  H03F2200/15 ,  H03F2200/411 ,  H03F2200/435 ,  H03F2200/465 ,  H03F2200/504 ,  H03G3/3042 ,  H04B1/0475

摘要： An amplifier circuit includes an amplifier, a detecting unit which detects a power output from the amplifier, a control unit which controls a saturation point of the amplifier with respect to a Peak-to-Average Power Ratio (PAPR) obtained by a detection output of the detecting unit.

摘要翻译： 放大器电路包括：放大器，检测从放大器输出的功率的检测单元;控制单元，其控制放大器的饱和点相对于通过检测输出获得的峰值平均功率比（PAPR） 检测单元。

公开(公告)号：US20120099624A1

公开(公告)日：2012-04-26

申请号：US13180590

申请日：2011-07-12

申请人： Setsuya NAGAYA ,  Akio Sasaki ,  Narito Matsuno ,  Kenji Iwai ,  Shinichi Kawai

发明人： Setsuya NAGAYA ,  Akio Sasaki ,  Narito Matsuno ,  Kenji Iwai ,  Shinichi Kawai

IPC分类号： H04B1/38

CPC分类号： H04B1/525

摘要： A communication device includes a transmitting circuit that includes a quadrature modulator; a receiving circuit that operates as a quadrature demodulator that, when being in a data non-transferring period, starts when power is switched on and ends when receiving operation starts, switches a local oscillator signal to a harmonic receiving signal, and detects the signal level of a harmonic included in a signal output from the transmitting circuit; a harmonic extracting circuit and a voltage control circuit that extract a harmonic from a modulated signal and adjust the harmonic so as to set the signal level less than or equal to a predetermined threshold. When being in the data non-transferring period, the transmitting circuit outputs a signal to the receiving circuit, the signal being generated by combining an amplified modulated signal with an under-adjustment signal.

摘要翻译： 一种通信装置，包括：包括正交调制器的发送电路; 作为正交解调器工作的接收电路，当处于数据非传送时段时，当接通电源并且在接收操作开始时结束时，该接收电路开始，将本地振荡器信号切换到谐波接收信号，并检测信号电平 包括在从发送电路输出的信号中的谐波; 谐波提取电路和电压控制电路，其从调制信号中提取谐波并调整谐波，以将信号电平设置为小于或等于预定阈值。 当处于数据非传送时段时，发送电路向接收电路输出信号，该信号通过将放大的调制信号与欠调制信号组合而产生。