摘要:
A communication device includes a transmitting circuit that includes a quadrature modulator; a receiving circuit that operates as a quadrature demodulator that, when being in a data non-transferring period, starts when power is switched on and ends when receiving operation starts, switches a local oscillator signal to a harmonic receiving signal, and detects the signal level of a harmonic included in a signal output from the transmitting circuit; a harmonic extracting circuit and a voltage control circuit that extract a harmonic from a modulated signal and adjust the harmonic so as to set the signal level less than or equal to a predetermined threshold. When being in the data non-transferring period, the transmitting circuit outputs a signal to the receiving circuit, the signal being generated by combining an amplified modulated signal with an under-adjustment signal.
摘要:
An amplifier circuit includes an amplifier, a detecting unit which detects a power output from the amplifier, a control unit which controls a saturation point of the amplifier with respect to a Peak-to-Average Power Ratio (PAPR) obtained by a detection output of the detecting unit.
摘要:
An effective range for a control voltage to operate a VCO is set in order to prevent the VCO from operating in the reverse characteristic area. A monitoring circuit is provided for monitoring the control voltage. When the control voltage is out of the effective range, the monitoring circuit outputs a monitor signal and inputs it into a charge pump. When the charge pump receives the monitor signal it generates a fixed voltage. Thus, when the reference signal is not inputted, the control voltage is maintained within a prespecified voltage range and the VCO oscillates within a prespecified frequency range.
摘要:
A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.