公开(公告)号：US20190043855A1

公开(公告)日：2019-02-07

申请号：US16147345

申请日：2018-09-28

申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L21/8249

CPC分类号： H01L27/0623 ,  H01L21/76229 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/737 ,  H01L29/7371

摘要： Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

公开(公告)号：US20180323186A1

公开(公告)日：2018-11-08

申请号：US15588011

申请日：2017-05-05

申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L29/737 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/161

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66242 ,  H01L29/737

摘要： Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

公开(公告)号：US20180323187A1

公开(公告)日：2018-11-08

申请号：US15658252

申请日：2017-07-24

申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L23/66 ,  H01L27/092 ,  H01L29/737 ,  H01L29/04 ,  H01L29/165 ,  H01L21/8249 ,  H01L21/762 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L27/0623 ,  H01L21/761 ,  H01L21/76229 ,  H01L21/8238 ,  H01L21/8249 ,  H01L23/66 ,  H01L27/092 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/7375

摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

公开(公告)号：US10062712B1

公开(公告)日：2018-08-28

申请号：US15660104

申请日：2017-07-26

申请人： Newport Fab, LLC

发明人： Kurt A. Moen ,  Paul D. Hurwitz

IPC分类号： H01L21/8234 ,  H01L27/12 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/02 ,  H01L21/84 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L27/02

CPC分类号： H01L27/1203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847

摘要： Methods for fabricating both PD-SOI devices and FD-SOI devices on the same semiconductor substrate are provided. The methods begin with a SOI wafer having a top silicon layer with a thickness appropriate for the fabrication of PD-SOI devices. During the fabrication process, portions of the top silicon layer, to be used for the fabrication of FD-SOI devices, are selectively thinned, so that a portion of the wafer has a top silicon thickness appropriate for FD-SOI devices. FD-SOI devices (e.g., RF switch transistors) are fabricated in the thinned portions of the top silicon layer, and PD-SOI devices (e.g., control transistors for the RF switch transistors) are fabricated in the non-thinned portions of the top silicon layer. Thus, both PD-SOI and FD-SOI devices can be combined within the same integrated circuit.

公开(公告)号：US10325907B2

公开(公告)日：2019-06-18

申请号：US16116816

申请日：2018-08-29

申请人： Newport Fab, LLC

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L23/66 ,  H01L27/092 ,  H01L29/737 ,  H01L29/04 ,  H01L29/165 ,  H01L21/8249 ,  H01L21/762 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/66

摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

公开(公告)号：US20180374842A1

公开(公告)日：2018-12-27

申请号：US16116816

申请日：2018-08-29

申请人： Newport Fab, LLC dba Jazz Semiconductor, Inc.

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/165 ,  H01L29/737 ,  H01L27/092 ,  H01L23/66 ,  H01L29/06 ,  H01L29/04

摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

公开(公告)号：US10347625B2

公开(公告)日：2019-07-09

申请号：US16147345

申请日：2018-09-28

申请人： Newport Fab, LLC

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/161 ,  H01L29/737 ,  H01L21/762 ,  H01L21/8238

摘要： Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

公开(公告)号：US10319716B2

公开(公告)日：2019-06-11

申请号：US15658252

申请日：2017-07-24

申请人： Newport Fab, LLC

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L23/66 ,  H01L27/092 ,  H01L29/737 ,  H01L29/04 ,  H01L29/165 ,  H01L21/8249 ,  H01L21/762 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/66

摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

公开(公告)号：US10290631B2

公开(公告)日：2019-05-14

申请号：US15588011

申请日：2017-05-05

申请人： Newport Fab, LLC

发明人： Kurt A. Moen ,  Edward J. Preisler ,  Paul D. Hurwitz

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L29/737 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/161

摘要： Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.