公开(公告)号：US5841482A

公开(公告)日：1998-11-24

申请号：US768361

申请日：1996-12-16

申请人： Niantsu N. Wang ,  Sherman Tan King ,  Guorjuh T. Hwang

发明人： Niantsu N. Wang ,  Sherman Tan King ,  Guorjuh T. Hwang

IPC分类号： G09G5/12 ,  H03K5/13 ,  H03L7/00 ,  H04N5/04 ,  H04N5/12 ,  H04N5/44 ,  H04N9/64 ,  H04N9/475

CPC分类号： G09G5/12 ,  H03K5/133 ,  H03L7/00 ,  H04N5/04 ,  H04N5/126 ,  G09G2340/125 ,  H04N5/4401 ,  H04N9/641

摘要： A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

摘要翻译： 同步系统对齐视频信号而不使用锁相环。 一个实施例包括延迟线和选择电路。 具有用于像素时钟的期望频率的时钟信号被施加到延迟线，以在延迟线上的抽头处产生一系列延迟信号。 当水平同步信号发生转换时，选择电路感测延迟的信号，并选择相对于水平同步信号中的跃迁具有对准的延迟信号。 该延迟信号是不受锁相环的频率波动影响的像素时钟信号。 在每个水平消隐期间选择一个新的延迟信号可以使每行视频的像素时钟与水平同步信号对齐。

公开(公告)号：US4808840A

公开(公告)日：1989-02-28

申请号：US123498

申请日：1987-11-20

申请人： Paul W. Chung ,  Niantsu N. Wang

发明人： Paul W. Chung ,  Niantsu N. Wang

IPC分类号： H03K3/356 ,  H03K3/013 ,  H03K3/15 ,  H03K3/295 ,  H03K3/86

CPC分类号： H03K3/356026

摘要： An edge-triggered latch is disclosed which has a low setup time and almost no metastability problem. It comprises a dynamic sensing means for detecting the voltage level of the data signal and at least one dynamic buffer for amplifying said detected voltage level into one of two logic levels recognizable by a static latch wherein the sampled result is stored.

公开(公告)号：US4859880A

公开(公告)日：1989-08-22

申请号：US207481

申请日：1988-06-16

申请人： Paul W. Chung ,  Niantsu N. Wang

发明人： Paul W. Chung ,  Niantsu N. Wang

IPC分类号： H03K5/02 ,  H03K5/151 ,  H03K17/687

CPC分类号： H03K5/151

摘要： A CMOS differential driver includes a differential amplifier with two input terminals. Complementary transfer gates selectively connect high and low voltage input terminals to the amplifier input terminals. The complementary transfer gates are controlled by identical logic input signals to provide exactly complementary voltage inputs to the differential amplifier circuit, so true complementary output signals are provided at the amplifier output terminals.