公开(公告)号：US5341033A

公开(公告)日：1994-08-23

申请号：US980247

申请日：1992-11-23

Applicant: Gregory T. Koker

Inventor： Gregory T. Koker

IPC: H03K3/013 ,  H03K3/3565 ,  H03K3/295

CPC classification number: H03K3/3565 ,  H03K3/013

Abstract: An input buffer circuit incorporates variable hysteresis levels to protect against unintended changes of output state in response to glitches in the input signal. The circuit is used in connection with input signals that alternate between LO and HI input states with known minimum periods between alternations. The switching threshold hysteresis for reverting back to a prior output state is boosted during the period following an input signal transition, with the boosted hysteresis removed following a delay period that is no greater than the minimum period between successive input signal transitions. Numerous circuit designs may be used to implement the varying hysteresis levels.

Abstract translation: 输入缓冲电路包含可变滞后电平，以防止输入信号中的毛刺响应输出状态的意外变化。 该电路与输入信号结合使用，该输入信号在LO和HI输入状态之间交替，在交替之间具有已知的最小周期。 在输入信号转换之后的周期期间，恢复到先前输出状态的开关阈值滞后被提升，其中在不大于连续输入信号转换之间的最小周期的延迟周期之后消除升压滞后。 可以使用许多电路设计来实现变化的滞后电平。

公开(公告)号：US5287014A

公开(公告)日：1994-02-15

申请号：US809526

申请日：1992-01-23

Applicant: Hitoshi Kinoshita

Inventor： Hitoshi Kinoshita

IPC: H03K3/2897 ,  H03K17/30 ,  H03K17/732 ,  H03K3/295 ,  H03K5/153 ,  H03K17/72

CPC classification number: H03K17/732 ,  H03K17/305

Abstract: A hysteresis circuit according to the invention has a thyristor circuit 101 which outputs a low voltage in an on-stage thereof, and outputs a high voltage in an off-state thereof. When an input voltage exceeds the threshold voltage of a first switching circuit 102, the circuit 102 turns on the thyristor circuit. On the other hand, when the input voltage exceeds the threshold voltage of a second switching circuit 103, the circuit 103 turns off the thyristor circuit.

Abstract translation: PCT No.PCT / JP91 / 00693 Sec。 371日期1992年1月23日 102（e）日期1992年1月23日PCT提交1991年5月23日PCT公布。 公开号WO91 / 19354 1991年12月12日。根据本发明的迟滞电路具有晶闸管电路101，其在其阶段输出低电压，并在其截止状态下输出高电压。 当输入电压超过第一开关电路102的阈值电压时，电路102接通晶闸管电路。 另一方面，当输入电压超过第二开关电路103的阈值电压时，电路103关断晶闸管电路。

公开(公告)号：US4786824A

公开(公告)日：1988-11-22

申请号：US613634

申请日：1984-05-24

Applicant: Eiji Masuda

Inventor： Eiji Masuda

IPC: H03K3/03 ,  H03K3/3565 ,  H03K3/013 ,  H03K3/15 ,  H03K3/295 ,  H03K3/86

CPC classification number: H03K3/3565 ,  H03K3/03

Abstract: An input signal level detecting circuit includes a first inverter group circuit having first and second inverters connected in series, and a second inverter group circuit having third and fourth inverters connected in series. The input terminals of the first and third inverters are supplied with a signal having first and second levels to be detected. The output terminals of the second and fourth inverters are connected to set and reset terminals of the flip-flop circuit. When the mean level of the first and second levels is V.sub.TM and the threshold voltages of the first to fourth inverters are V.sub.T1 to V.sub.T4, respectively, the relations V.sub.T1 >V.sub.TM ; V.sub.T2 T.sub.TM are satisfied.

Abstract translation: 输入信号电平检测电路包括具有串联连接的第一和第二反相器的第一反相器组电路和具有串联连接的第三和第四反相器的第二反相器组电路。 第一和第三反相器的输入端被提供有要检测的第一和第二电平的信号。 第二和第四反相器的输出端子连接到触发器电路的设置和复位端子。 当第一级和第二级的平均电平分别为VTM，第一至第四反相器的阈值电压分别为VT1至VT4时，关系VT1> VTM; VT2 TTM。

公开(公告)号：US4694198A

公开(公告)日：1987-09-15

申请号：US890263

申请日：1986-07-29

Applicant: Yoshitaka Umeki

Inventor： Yoshitaka Umeki

IPC: H03K3/2893 ,  H03K3/2897 ,  H03K3/295

CPC classification number: H03K3/2893

Abstract: A Schmitt trigger circuit comprising input and output terminals, first and second voltage supply lines, a first transistor having its base connected to the input terminal and its the collector connected to the first voltage supply line though a load resistor, a second transistor having its collector connected to the first voltage supply line, a first constant-current source through which the first and second transistors have their respective emitters commonly connected to the second supply voltage line, and a third transistor having its collector connected to the first voltage supply line, its base connected to the first voltage supply line through the load resistor and to the collector of the first transistor and its emitter connected to the base of the second transistor. There is further provided a second constant-current source through which the third transistor has its base further connected to the second voltage supply line.

Abstract translation: 施密特触发电路包括输入和输出端子，第一和第二电压供应线路，第一晶体管的基极连接到输入端子，其集电极通过负载电阻器连接到第一电压供应线路，第二晶体管具有其集电极 连接到所述第一电压源线，第一恒流源，所述第一和第二晶体管通过所述第一恒流源具有共同连接到所述第二电源电压线的各自的发射极;以及第三晶体管，其集电极连接到所述第一电压供应线， 基极通过负载电阻连接到第一电压线，并连接到第一晶体管的集电极，其发射极连接到第二晶体管的基极。 还提供了第二恒流源，第三晶体管的基极通过第二恒流源进一步连接到第二电压源线。

公开(公告)号：US4668881A

公开(公告)日：1987-05-26

申请号：US556932

申请日：1983-12-01

Applicant: Douglas S. Piasecki

Inventor： Douglas S. Piasecki

IPC: H03K3/286 ,  H03K3/2885 ,  H03K5/153 ,  H03K3/033 ,  H03K3/295

CPC classification number: H03K3/2865 ,  H03K3/2885

Abstract: A circuit whose output is asymmetrical whereby the circuit makes a transition from a first state to a second state more slowly than from the second state to the first state a preset towards the second state prior to the application of data input signals to the circuit.

Abstract translation: 其输出不对称的电路，由此电路在从数据输入信号施加到电路之前，从第二状态向第一状态缓慢地向第二状态预设。

公开(公告)号：US4596939A

公开(公告)日：1986-06-24

申请号：US525753

申请日：1983-08-23

Applicant: Tatsuo Yamada

Inventor： Tatsuo Yamada

IPC: H03F1/26 ,  H03K3/353 ,  H03K5/1252 ,  H03K3/295

CPC classification number: H03K5/1252

Abstract: An input amplifier circuit, specifically, an input amplifier circuit for logic signals, in which noise signal components having a duration less than a predetermined duration are eliminated from the output signal of the amplifier. A delay circuit is added to the feedback loop of a Schmitt trigger amplifier circuit which has a delay time equal to the predetermined delay. The delay circuit effectively inhibits the output signal from changing state unless the input signal has a duration greater than the predetermined duration.

Abstract translation: 输入放大器电路，具体地说，用于逻辑信号的输入放大器电路，其中具有小于预定持续时间的持续时间的噪声信号分量从放大器的输出信号中消除。 延迟电路被添加到施密特触发放大器电路的反馈回路中，其具有等于预定延迟的延迟时间。 延迟电路有效地抑制输出信号改变状态，除非输入信号具有大于预定持续时间的持续时间。

公开(公告)号：US4539489A

公开(公告)日：1985-09-03

申请号：US506745

申请日：1983-06-22

Applicant: Herchel A. Vaughn

Inventor： Herchel A. Vaughn

IPC: H03K3/3565 ,  H03K3/356 ,  H03K3/295

CPC classification number: H03K3/3565

Abstract: A CMOS Schmitt trigger which has two series-connected inverters uses both an input and an output signal to provide hysteresis. A pair of series-coupled transistors is coupled between a power supply terminal and a node between the two inverters. One of the transistors has a control electrode for receiving the input signal. The other of the transistors has a control electrode for receiving the output signal.

Abstract translation: 具有两个串联连接的逆变器的CMOS施密特触发器使用输入和输出信号来提供迟滞。 一对串联耦合晶体管耦合在两个逆变器之间的电源端子和节点之间。 其中一个晶体管具有用于接收输入信号的控制电极。 另一个晶体管具有用于接收输出信号的控制电极。

公开(公告)号：US4409495A

公开(公告)日：1983-10-11

申请号：US268643

申请日：1981-05-29

Applicant: Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

Inventor： Hiromu Enomoto ,  Yoshiharu Mitono ,  Yasushi Yasuda ,  Taketo Imaizumi ,  Hiroshi Ohta

IPC: H03K3/2893 ,  H03K5/08 ,  H03K3/295

CPC classification number: H03K3/2893

Abstract: A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

Abstract translation: 施密特触发电路具有降低噪声灵敏度和防止振荡的输入电压滞后特性。 在其输入级具有多发射极晶体管，并且在其输出级中具有第二晶体管。 多发射极晶体管包括第一发射极和第二发射极。 响应于施加到多发射极晶体管的基极的输入电压，第一发射极与开关操作相关联。 第二发射极与从第二晶体管的基极通过多发射极晶体管的基极到地的绘制电荷的操作相关联。 使用多发射极晶体管可防止输入电流随着输入电压的下降而大幅度增加。

公开(公告)号：US4301379A

公开(公告)日：1981-11-17

申请号：US85827

申请日：1979-10-17

Applicant: John R. Reinert

Inventor： John R. Reinert

IPC: G06F13/37 ,  H03K3/2893 ,  H03K3/295

CPC classification number: H03K3/2893 ,  G06F13/37

Abstract: A basic Schmitt trigger circuit is modified with additional circuit components for a two-input bistable circuit (latch). The latching Schmitt trigger circuit exhibits enhanced operating characteristics, such as fast and reliable switching between stable states. Also the circuit is compatible with design parameters and operating tolerances of integrated circuits. The latching Schmitt trigger circuit enables implementation of a fast reliable arbitration circuit in an integrated circuit version by minimizing the necessary time delay between the end of a resource request signal period and the start of an interrogate signal period.

Abstract translation: 基本的施密特触发电路通过用于双输入双稳态电路（锁存器）的附加电路元件进行修改。 锁存施密特触发电路具有增强的工作特性，例如稳定状态之间的快速可靠的切换。 此外，该电路与集成电路的设计参数和工作容差兼容。 锁存施密特触发电路能够通过最小化资源请求信号周期结束与询问信号周期开始之间的必要时间延迟来实现集成电路版本中的快速可靠仲裁电路。

公开(公告)号：US4161703A

公开(公告)日：1979-07-17

申请号：US886395

申请日：1978-03-14

Applicant: Karl-Diether Nutz

Inventor： Karl-Diether Nutz

IPC: H03K3/03 ,  H03K3/295 ,  H03K3/35

CPC classification number: H03K3/03

Abstract: An oscillator for producing rectangular pulses comprises a Schmitt trigger controlled by an R.C. element connected in series, a constant current source for charging up the capacitor and a current image circuit for ensuring that the discharge current of the capacitor is consistent with its charging current.

Abstract translation: 用于产生矩形脉冲的振荡器包括由R.C.控制的施密特触发器。 串联连接的元件，用于对电容器充电的恒流源和用于确保电容器的放电电流与其充电电流一致的当前图像电路。