公开(公告)号：US20120305928A1

公开(公告)日：2012-12-06

申请号：US13565035

申请日：2012-08-02

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/786

CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

摘要： A Field Effect Transistor (FET) device includes a gate stack formed over a channel region, a source region adjacent to the channel region, wherein a portion of a boundary between the source region and the channel region is defined along a plane defined by a sidewall of the gate stack, a drain region adjacent to the channel region, a portion of the drain region arranged below the gate stack, a native oxide layer disposed over a portion of the source region, along sidewalls of the gate stack, and over a portion of the drain region, a spacer arranged over a portion of the native oxide layer above the source region and the drain region and along the native oxide layer along the sidewalls of the gate stack.

摘要翻译： 场效应晶体管（FET）器件包括形成在通道区域上的栅极堆叠，与沟道区域相邻的源极区域，其中源极区域和沟道区域之间的边界的一部分沿着由侧壁 栅极堆叠的漏极区域，与沟道区域相邻的漏极区域，布置在栅极堆叠下方的漏极区域的一部分，沿着栅极堆叠的侧壁设置在源极区域的一部分上的自然氧化物层， 漏极区域上的间隔物，其间隔设置在源极区域和漏极区域上方的自然氧化物层的一部分上，并且沿着栅极叠层的侧壁沿着天然氧化物层。

公开(公告)号：US20110278673A1

公开(公告)日：2011-11-17

申请号：US12779100

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/786 ,  H01L21/306

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20110278580A1

公开(公告)日：2011-11-17

申请号：US12779079

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L21/311

CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

摘要： A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造积极缩放CMOS器件的凹陷源区的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控制地在薄体的沟道中形成远远小于40nm的器件的源极的凹陷区域，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US08716798B2

公开(公告)日：2014-05-06

申请号：US12779100

申请日：2010-05-13

申请人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20130012026A1

公开(公告)日：2013-01-10

申请号：US13611678

申请日：2012-09-12

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L21/311

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20110278672A1

公开(公告)日：2011-11-17

申请号：US12779087

申请日：2010-05-13

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L27/12 ,  H01L21/302

CPC分类号： H01L27/092 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66757

摘要： A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造积极缩放的CMOS器件的凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控地形成薄体的沟道中的漏极的凹陷区域，远小于40nm的器件，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向异性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US09006108B2

公开(公告)日：2015-04-14

申请号：US13611678

申请日：2012-09-12

申请人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/84 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848

摘要： A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造大型CMOS器件的凹陷源极和凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后是等离子体蚀刻的处理顺序可控制地形成薄体的通道中的源极和漏极的凹陷区域，远小于40nm的器件，以实现随后的外延生长 SiGe，SiC或其他材料，从而导致器件和环形振荡器性能的提高。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US20140231809A1

公开(公告)日：2014-08-21

申请号：US13565030

申请日：2012-08-02

申请人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C. Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L29/786

CPC分类号： H01L29/78675 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78654

摘要： A Field Effect Transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer.

摘要翻译： 场效应晶体管器件包括掩埋氧化物层，掩埋氧化物层上方的硅层，各向同性凹陷源极区域和包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US08431995B2

公开(公告)日：2013-04-30

申请号：US12779087

申请日：2010-05-13

申请人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

发明人： Nicholas C Fuller ,  Steve Koester ,  Isaac Lauer ,  Ying Zhang

IPC分类号： H01L27/12

CPC分类号： H01L27/092 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66757

摘要： A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

摘要翻译： 一种用于制造积极缩放的CMOS器件的凹陷漏极区域的方法。 在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控地形成薄体的沟道中的漏极的凹陷区域，远小于40nm的器件，以使SiGe，SiC的后续外延生长 ，或其他材料，并且随之而来的器件和环形振荡器性能的增加。 还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的漏极区域; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

公开(公告)号：US06177289B1

公开(公告)日：2001-01-23

申请号：US09205433

申请日：1998-12-04

申请人： John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

发明人： John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

IPC分类号： H01L2166

CPC分类号： H01L31/03529 ,  H01L31/035281 ,  H01L31/105 ,  Y02E10/50

摘要： A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.

摘要翻译： 单片半导体光检测器形成在其上蚀刻有多个基本上平行的沟槽的衬底上。 沟槽还形成为由作为N沟道区域和P沟道区域之间的I区域的基板的柱状区域分离的多个交替的N型和P型沟槽区域。 第一和第二触点形成在衬底的表面上并分别互连N型沟槽区和P型沟槽区。 优选地，以与检测器响应的光辐射的光消光长度相当的深度蚀刻沟槽。