公开(公告)号：US07932103B2

公开(公告)日：2011-04-26

申请号：US11680568

申请日：2007-02-28

Applicant: Niraj Subba ,  Jung-Suk Goo

Inventor： Niraj Subba ,  Jung-Suk Goo

IPC: G01R31/26

CPC classification number: H01L22/14

Abstract: An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof.

Abstract translation: 一种集成电路系统，包括测量基栅和基底连接器之间的基底结构的电容，测量测试栅和测试连接器之间的测试结构的电容，具有测试栅的测试结构，测试电介质和 所述测试连接器具有延伸到其下的测试电介质，并且确定所述基底结构和所述测试结构的电容之间的差异，以确定所述基极栅极与所述基极连接器之间的基底结构的寄生电容。

公开(公告)号：US20080204052A1

公开(公告)日：2008-08-28

申请号：US11680568

申请日：2007-02-28

Applicant: Niraj Subba ,  Jung-Suk Goo

Inventor： Niraj Subba ,  Jung-Suk Goo

IPC: G01R27/26 ,  G06F17/50

CPC classification number: H01L22/14

Abstract: An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof.

Abstract translation: 一种集成电路系统，包括测量基栅和基底连接器之间的基底结构的电容，测量测试栅和测试连接器之间的测试结构的电容，具有测试栅的测试结构，测试电介质和 所述测试连接器具有延伸到其下的测试电介质，并且确定所述基底结构和所述测试结构的电容之间的差异，以确定所述基极栅极与所述基极连接器之间的基底结构的寄生电容。

公开(公告)号：US20080054316A1

公开(公告)日：2008-03-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US20060099752A1

公开(公告)日：2006-05-11

申请号：US10986399

申请日：2004-11-10

Applicant: Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US08502283B2

公开(公告)日：2013-08-06

申请号：US11926655

申请日：2007-10-29

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L29/78

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US07306997B2

公开(公告)日：2007-12-11

申请号：US10986399

申请日：2004-11-10

Applicant: Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

Inventor： Qi Xiang ,  Niraj Subba ,  Witold P. Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC: H01L21/336

CPC classification number: H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

Abstract: A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

Abstract translation: 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US20100010798A1

公开(公告)日：2010-01-14

申请号：US12217793

申请日：2008-07-09

Applicant: Vineet Wason ,  Sushant Suryagandh ,  Zhi-Yuan Wu ,  Priyanka Chiney ,  Niraj Subba

Inventor： Vineet Wason ,  Sushant Suryagandh ,  Zhi-Yuan Wu ,  Priyanka Chiney ,  Niraj Subba

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.

Abstract translation: 本方法是在晶体管模型中对漏极诱导的栅极降低（DIBL）建模的方法，晶体管模型基于MOSFET晶体管。 晶体管模型包括基极，源极，漏极，栅极和栅极端子。 在本方法中，向栅极端子施加电压，向漏极施加电压，并且在栅极端子与栅极之间施加电位。 施加在栅极端子和栅极之间的电位的大小与施加到漏极的电压的大小成比例地变化。