公开(公告)号：US07989289B2

公开(公告)日：2011-08-02

申请号：US12165272

申请日：2008-06-30

申请人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

发明人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

摘要翻译： 通常描述浮栅结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率 以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率 。 与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

公开(公告)号：US20090321809A1

公开(公告)日：2009-12-31

申请号：US12165219

申请日：2008-06-30

申请人： Nirmal Ramaswamy ,  Tejas Krishnamohan ,  Kyu Min ,  Thomas M. Graettinger

发明人： Nirmal Ramaswamy ,  Tejas Krishnamohan ,  Kyu Min ,  Thomas M. Graettinger

IPC分类号： H01L29/788 ,  H01L21/469

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02145 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/3143 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513

摘要： Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed.

摘要翻译： 简而言之，公开了一种用于包括梯度氧化氮层的非易失性存储器件的隧道势垒。

公开(公告)号：US20090283817A1

公开(公告)日：2009-11-19

申请号：US12165272

申请日：2008-06-30

申请人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

发明人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

摘要翻译： 通常描述浮栅结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率 以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率 。 与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

公开(公告)号：US20090001443A1

公开(公告)日：2009-01-01

申请号：US11771482

申请日：2007-06-29

申请人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

发明人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

摘要： Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.

摘要翻译： 公开了一种非易失性存储单元。 非易失性存储单元包括具有有源区的基板。 底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。 电荷存储节点设置在底部电介质层的上方。 此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。 多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。 在多个顶部电介质层中，设置有控制栅极。

公开(公告)号：US07705389B2

公开(公告)日：2010-04-27

申请号：US11847183

申请日：2007-08-29

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

公开(公告)号：US08643082B2

公开(公告)日：2014-02-04

申请号：US13276600

申请日：2011-10-19

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

公开(公告)号：US20090057744A1

公开(公告)日：2009-03-05

申请号：US11847183

申请日：2007-08-29

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

公开(公告)号：US20120032252A1

公开(公告)日：2012-02-09

申请号：US13276600

申请日：2011-10-19

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

公开(公告)号：US08058140B2

公开(公告)日：2011-11-15

申请号：US12757869

申请日：2010-04-09

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L21/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

公开(公告)号：US20100197131A1

公开(公告)日：2010-08-05

申请号：US12757869

申请日：2010-04-09

申请人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

发明人： Ron Weimer ,  Kyu Min ,  Tom Graettinger ,  Nirmal Ramaswamy

IPC分类号： H01L21/302

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

摘要翻译： 公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。 在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。 一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。 在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。 在一些实施例中，电荷捕获结构包括纳米点。 在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。