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    NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC
    1.
    发明申请
    NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC 审中-公开
    具有多层阻塞介质的非易失性存储单元

    公开(公告)号：US20090001443A1

    公开(公告)日：2009-01-01

    申请号：US11771482

    申请日：2007-06-29

    申请人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

    发明人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

    IPC分类号： H01L29/788

    CPC分类号： H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

    摘要： Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.

    摘要翻译： 公开了一种非易失性存储单元。 非易失性存储单元包括具有有源区的基板。 底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。 电荷存储节点设置在底部电介质层的上方。 此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。 多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。 在多个顶部电介质层中，设置有控制栅极。

    Memory Cells
    2.
    发明申请
    Memory Cells 有权
    记忆细胞

    公开(公告)号：US20110133268A1

    公开(公告)日：2011-06-09

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

    Memory cells containing charge-trapping zones
    4.
    发明授权
    Memory cells containing charge-trapping zones 有权
    含有电荷捕获区的存储单元

    公开(公告)号：US08228743B2

    公开(公告)日：2012-07-24

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。