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    Apparatus and method for caching lock conditions in a multi-processor system
    6.
    发明授权
    Apparatus and method for caching lock conditions in a multi-processor system 失效
    用于在多处理器系统中缓存锁定条件的装置和方法

    公开(公告)号：US6006299A

    公开(公告)日：1999-12-21

    申请号：US204592

    申请日：1994-03-01

    申请人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Mandar S. Joshi ,  Nitin V. Sarangdhar ,  Matthew A. Fisch

    发明人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Mandar S. Joshi ,  Nitin V. Sarangdhar ,  Matthew A. Fisch

    IPC分类号： G06F9/46 ,  G06F13/08

    CPC分类号： G06F9/52

    摘要： In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.

    摘要翻译： 在计算机系统中，一种用于处理锁定条件的装置，其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据，同时执行也处理该相同数据的第二指令。 当第一个处理器开始执行第一个指令时，锁定位被置位。 于是，第二处理器被阻止执行其指令，直到第一处理器完成对共享数据的处理。 因此，第二处理器将其请求排队在缓冲器中。 在第一个处理器完成其指令执行后，锁定位被清零。 然后，第一个处理器检查缓冲区是否有任何未完成的请求。 响应于第二处理器的排队请求，第一处理器向第二处理器发送指示数据现在不被锁定的信号。

    Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system
    7.
    发明授权
    Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system 失效
    用于在多处理器计算机系统中维持多级高速缓存层级一致性的装置

    公开(公告)号：US5715428A

    公开(公告)日：1998-02-03

    申请号：US639719

    申请日：1996-04-29

    申请人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

    发明人： Wen-Hann Wang ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Nitin V. Sarangdhar ,  John M. Bauer ,  Mandar S. Joshi ,  Ashwani K. Gupta

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0831 ,  G06F12/0811

    摘要： A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions. State transitions depend on both processor generated activities and activities by other bus agents, including other processors. Data consistency is guaranteed in systems having multiple levels of cache and shared memory and/or multiple active agents, such that no agent ever reads stale data and actions are serialized as needed.

    摘要翻译： 一种计算机系统，包括具有高速缓存层级的多个高速缓存代理，所述高速缓存代理器通过系统总线共享存储器并根据协议发出存储器访问请求，其中高速缓存行具有包括多条线路之一的当前状态 状态。 多个行状态包括修改的（M）状态，其中M状态的第一高速缓存代理的行具有比系统中的任何其他副本更新的数据; 排除（E）状态，其中第一高速缓存代理中的E状态中的线是系统中唯一具有高速缓存行中的数据的副本的代理，第一高速缓存代理将数据修改为 所述高速缓存行独立于耦合到所述系统总线的其它所述代理; 共享（S）状态，其中S状态的行指示多于一个代理具有该行中的数据的副本; 和指示该行不存在于缓存中的无效（I）状态。 对I状态的行进行读取或写入会导致高速缓存未命中。 本发明将状态与线相关联并且定义了管理状态转换的规则。 状态转换取决于处理器生成的活动和其他总线代理（包括其他处理器）的活动。 在具有多级缓存和共享内存和/或多个活动代理的系统中保证数据一致性，使得任何代理程序都不会读取过时的数据，并且操作根据需要进行序列化。

    Computer system with distributed bus arbitration scheme for symmetric and priority agents
    8.
    发明授权
    Computer system with distributed bus arbitration scheme for symmetric and priority agents 失效
    具有分布式总线仲裁方案的计算机系统，用于对称和优先代理

    公开(公告)号：US5581782A

    公开(公告)日：1996-12-03

    申请号：US538597

    申请日：1995-10-03

    申请人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

    发明人： Nitin V. Sarangdhar ,  Konrad K. Lai ,  Gurbir Singh ,  Michael W. Rhodehamel ,  Matthew A. Fisch

    IPC分类号： G06F13/36 ,  G06F13/364 ,  H04L12/403 ,  G06F13/18

    CPC分类号： G06F13/364 ,  G06F13/36 ,  H04L12/403 ,  H04L12/4015

    摘要： A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner). The symmetric owner is allowed to take ownership of the bus and issue a transaction on the bus provided no other action of higher priority is preventing the use of the bus. A symmetric owner can maintain ownership without re-arbitrating if the transaction is either a bus-locked or a burst access transaction. The priority agent(s) has higher priority than the symmetric owner. Once the priority agent arbitrates for the bus, it prevents the symmetric owner from issuing any new transactions on the bus unless the new transaction is part of an ongoing bus-locked operation.

    摘要翻译： 一种用于提供包括对优先代理的支持的高性能对称仲裁协议的系统和方法。 总线仲裁协议支持两类总线代理：对称代理和优先代理。 对称代理使用循环算法支持公平的分布式仲裁。 每个对称代理都具有在复位时分配的唯一代理ID。 该算法按照循环顺序排列对称代理。 每个对称代理还维持忙或空闲的总线所有权状态以及在下一个仲裁事件中反映具有最低优先级的对称代理的旋转ID。 在仲裁事件中，优先级最高的对称代理成为对称所有者。 然而，对称所有者不一定是总线总线所有者（即，优先代理可以是总线总线所有者）。 允许对称所有者获得公共汽车的所有权，并在公共汽车上发出交易，只要没有更高优先级的其他动作阻止使用公共汽车。 如果事务是总线锁定或突发访问事务，对称所有者可以维护所有权而不重新仲裁。 优先级代理的优先级高于对称所有者。 一旦优先级代理对总线进行仲裁，就可以防止对称所有者在总线上发出任何新的事务，除非新的事务是持续的总线锁定操作的一部分。

    Method and apparatus for cache memory replacement line identification
    10.
    发明授权
    Method and apparatus for cache memory replacement line identification 失效
    用于高速缓存存储器替换线路识别的方法和装置

    公开(公告)号：US5809524A

    公开(公告)日：1998-09-15

    申请号：US822044

    申请日：1997-03-24

    申请人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

    发明人： Gurbir Singh ,  Wen-Hann Wang ,  Michael W. Rhodehamel ,  John M. Bauer ,  Nitin V. Sarangdhar

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/123 ,  G06F12/0831

    摘要： A method and apparatus for cache memory replacement line identification have a cache interface which provides a communication interface between a cache memory and a controller for the cache memory. The interface includes an address bus, a data bus, and a status bus. The address bus transfers requested addresses from the controller to the cache memory. The data bus transfers data associated with requested addresses from the controller to the cache memory, and also transfers replacement line addresses from the cache memory to the controller. The status bus transfers status information associated with the requested addresses from the cache memory to the controller which indicate whether the requested addresses are contained in the cache memory. In one embodiment, the data bus also transfers cache line data associated with a requested address from the cache memory to the controller when the requested address hits the cache memory.

    摘要翻译： 一种用于高速缓存存储器替代线路识别的方法和装置具有缓存接口，其提供高速缓冲存储器和用于高速缓冲存储器的控制器之间的通信接口。 该接口包括地址总线，数据总线和状态总线。 地址总线将请求的地址从控制器传送到高速缓冲存储器。 数据总线将与请求的地址相关联的数据从控制器传送到高速缓冲存储器，并且还将替换行地址从高速缓冲存储器传送到控制器。 状态总线将与请求的地址相关联的状态信息从高速缓冲存储器传送到控制器，该控制器指示所请求的地址是否包含在高速缓冲存储器中。 在一个实施例中，当请求的地址与高速缓冲存储器匹配时，数据总线还将与所请求的地址相关联的高速缓存行数据从高速缓冲存储器传送到控制器。