公开(公告)号：US07099628B2

公开(公告)日：2006-08-29

申请号：US10963603

申请日：2004-10-14

申请人： Noam Galperin ,  Ariel Zohar ,  Yonatan Manor ,  Rafi Retter

发明人： Noam Galperin ,  Ariel Zohar ,  Yonatan Manor ,  Rafi Retter

IPC分类号： H04B17/00

CPC分类号： H04L25/03146 ,  H04L2025/03382 ,  H04L2025/0349 ,  H04L2025/03605 ,  H04L2025/03789

摘要： A system and method for enhancing the reception of a single carrier signal. The single carrier signal includes periodic training signal and data. The system includes a transmitter configured such that L symbols of either the beginning or end of the N symbols of the training signal, where L

摘要翻译： 一种用于增强单载波信号的接收的系统和方法。 单载波信号包括周期训练信号和数据。 该系统包括发射机，其配置为使得训练信号的N个符号的开始或结尾的L个符号（其中L

公开(公告)号：US5995157A

公开(公告)日：1999-11-30

申请号：US16943

申请日：1998-02-02

申请人： Rafi Retter ,  Yonatan Manor ,  David Bar

发明人： Rafi Retter ,  Yonatan Manor ,  David Bar

IPC分类号： H04N5/08 ,  H04N5/10 ,  H04N5/21 ,  H04N5/46 ,  H04N9/64 ,  H04N5/04

CPC分类号： H04N5/08 ,  H04N5/211 ,  H04N5/46 ,  H04N9/642

摘要： In a composite video signal that contains an image field having vertical synchronization (V.sub.-- Sync) pulses, The V.sub.-- sync pulses include first equalization pulses of E.sub.1 waveforms followed by a serration pulses of S waveforms, T.sub.S -long each, followed by a second equalization pulse of E.sub.2 waveforms, T.sub.E -long each. The transition from a last waveform of the E.sub.1 waveforms to a first waveform of the S waveforms constitutes a vertical synchronization (V.sub.-- sync) signal. The system a reference event occurring at a first time interval .DELTA.T .sub.1 .+-.Er after said V.sub.-- sync signal, wherein Er stands for time shift error. The system includes filter for filtering the composite video signal so as to obtain a filtered signal. Clamper for clamping the filtered signal so as to obtain a clamped signal. First detector for detecting N (N.ltoreq.S) waveforms in the serration pulses thereby indicating first event occurrence. Second detector for detecting M (M.ltoreq.E.sub.2) waveforms in the second equalization pulses, thereby determining the reference event occurrence, such that the .DELTA.T .sub.1 equals M*T.sub.E +S*T.sub.S.

摘要翻译： 在包含具有垂直同步（V-Sync）脉冲的图像场的复合视频信号中，V同步脉冲包括E1波形的第一均衡脉冲，随后是S波形的锯齿脉冲，每个TS-长，随后是第二 E2波形的均衡脉冲，TE长。 从E1波形的最后波形到S波形的第一波形的转换构成垂直同步（V-sync）信号。 所述系统在所述V同步信号之后以第一时间间隔DELTA T 1 +/- Er发生参考事件，其中Er表示时移误差。 该系统包括用于对复合视频信号进行滤波以获得滤波信号的滤波器。 钳位器用于钳位滤波后的信号，以获得钳位信号。 第一检测器，用于检测锯齿脉冲中的N（N

公开(公告)号：US06021421A

公开(公告)日：2000-02-01

申请号：US802083

申请日：1997-02-19

申请人： Rafi Retter ,  Yonatan Manor ,  David Bar ,  Shlomo Mahlab ,  Ronny Aboutboul

发明人： Rafi Retter ,  Yonatan Manor ,  David Bar ,  Shlomo Mahlab ,  Ronny Aboutboul

IPC分类号： G06F17/10 ,  G06F17/15

CPC分类号： G06F17/10

摘要： An enhanced digital signal processor (EDSP) includes execution section that includes the following constituents: a processor, an arithmetic logic unit (ALU), a memory device for holding set of instructions for execution selected from enhanced set of instructions, a memory device for holding data, another clock generator for generating a plurality of clock signals coupled to above constituents. Internal communication bus coupled to the above constituents for affording controlled communication between them, a correlator, coupled to the bus, for communication with the execution section. The correlator having an input port for receiving external input data and an output port for outputting data. The correlator being controlled by the processor and being responsive to the selected instruction from the enhanced set of instructions, for operating in the following mode: correlator processing mode wherein the correlator receives data from the above constituents and outputs data to the constituents, and wherein the input data received through the input port, is transmitted to the output port in an intact form.

摘要翻译： 增强型数字信号处理器（EDSP）包括执行部分，其包括以下组成部分：处理器，算术逻辑单元（ALU），用于保持用于执行的用于执行的增强指令集的指令的存储器装置，用于保持 数据，另一个时钟发生器，用于产生耦合到上述组成部分的多个时钟信号。 内部通信总线耦合到上述组件以提供它们之间的受控通信，耦合到总线的相关器，用于与执行部分通信。 相关器具有用于接收外部输入数据的输入端口和用于输出数据的输出端口。 所述相关器由所述处理器控制并且响应来自所述增强指令集的所选择的指令，以在以下模式下操作：相关器处理模式，其中所述相关器从所述组成部分接收数据并向所述组成部分输出数据，并且其中， 通过输入端口接收的输入数据以完整的形式传输到输出端口。

公开(公告)号：US5053985A

公开(公告)日：1991-10-01

申请号：US424079

申请日：1989-10-19

申请人： Rami Friedlander ,  Rafi Retter

发明人： Rami Friedlander ,  Rafi Retter

IPC分类号： G06F17/14 ,  G06T9/00

CPC分类号： G06F17/147 ,  G06T9/007

摘要： A discrete cosine transform/inverse discrete cosine transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

公开(公告)号：US4547849A

公开(公告)日：1985-10-15

申请号：US615081

申请日：1984-08-17

申请人： Glenn Louie ,  Rafi Retter ,  James Slager

发明人： Glenn Louie ,  Rafi Retter ,  James Slager

IPC分类号： G06F9/38 ,  G06F15/17 ,  G06F15/16

CPC分类号： G06F15/17 ,  G06F9/3879

摘要： A nonclock-synchronous interface between a microprocessor and a coprocessor. A request line (404) from the coprocessor and an acknowledgment line (402) from the microprocessor provide for operand transfer from the coprocessor to the microprocessor. A busy line (410) and an error line (408) from the coprocessor allow the microprocessor to monitor the condition of the coprocessor. Data (406) are transferred through a data channel in the microprocessor using the full memory management and protection mechanism of the microprocessor so that the protection mechanism is not circumvented. A memory-read cycle is generated using the address taken from the memory-address register (401). The data is buffered inside the microprocessor and the coprocessor's request is acknowledged. The memory-address register is then incremented by a predetermined amount and an I/O write cycle is generated using a prewired address into the coprocessor. Data are transferred in the opposite direction in a similar manner using the prewired address to obtain the read data from the coprocessor which data is buffered inside of the microprocessor. A memory-write cycle is then generated by the processor using an address taken from the channel memory-address register and the data equal to the data buffered.

摘要翻译： 微处理器与协处理器之间的非时钟同步接口。 来自协处理器的请求线（404）和来自微处理器的确认线（402）提供从协处理器到微处理器的操作数传送。 来自协处理器的忙线（410）和错误线（408）允许微处理器监视协处理器的状况。 数据（406）通过微处理器中的数据通道使用微处理器的完整存储器管理和保护机制传送，从而避免了保护机制。 使用从存储器地址寄存器（401）获取的地址生成存储器读取周期。 数据缓冲在微处理器内部，协处理器的请求得到确认。 然后将存储器地址寄存器递增预定量，并且使用预编程地址生成到协处理器中的I / O写入周期。 数据以相似的方式使用预接地址以相反的方式传送，以从协处理器获得读取的数据，该数据被缓冲在微处理器的内部。 然后由处理器使用从通道存储器地址寄存器获取的地址和等于数据缓冲的数据产生存储器 - 写入周期。

公开(公告)号：US5179530A

公开(公告)日：1993-01-12

申请号：US711573

申请日：1991-05-31

申请人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Vlad Fruchter ,  Ricardo Jaliff ,  Asaf Mohr ,  Rafi Retter

发明人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Vlad Fruchter ,  Ricardo Jaliff ,  Asaf Mohr ,  Rafi Retter

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/10

CPC分类号： G06F9/30014 ,  G06F15/8076 ,  G06F17/10 ,  G06F9/3004 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3885

摘要： Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.

摘要翻译： 矢量信号处理器中提供多个专用处理单元，用于并行，并行处理，特别是复杂矢量。 主处理单元是执行单元，数据移动单元，控制/寄存单元，向量缓冲单元，指令获取单元和总线接口单元。