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公开(公告)号：US07630243B2
公开(公告)日：2009-12-08
申请号：US12094379
申请日：2006-11-01
申请人： Kaoru Yamamoto , Nobuhiko Ito , Naoki Ueda , Yoshimitsu Yamauchi
发明人： Kaoru Yamamoto , Nobuhiko Ito , Naoki Ueda , Yoshimitsu Yamauchi
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/24 , G11C16/26
摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.
摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。
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2.发明授权公开(公告)号：US07224611B2
公开(公告)日：2007-05-29
申请号：US11173925
申请日：2005-07-01
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/0491 , G11C16/24
摘要： A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
摘要翻译： 具有虚拟接地线型存储器阵列结构的半导体存储器件包括读出电路，用于选择连接到要读取的存储单元的源极和漏极的一对选定位线，将预定电压施加在成对选定位之间 并且感测流过待读取的存储单元的存储单元电流，以及用于从中间节点电位产生的逆电位产生电路，该中间节点电位高于所选位线上的电位的任何电平，并从中间层 在电流路径上用于馈送读出电路中的存储单元电流的一个节点，根据存储单元电流使与中间节点电位相同的方向变化的反电位，使得其变化大于中间节点电位的变化 ，其中所述计数器电位被施加到在所选择的所述配对的高电平处的一个旁边分配的未选位线 位线。
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公开(公告)号：US20050135161A1
公开(公告)日：2005-06-23
申请号：US11013119
申请日：2004-12-14
CPC分类号： G11C7/1069 , G11C7/062 , G11C7/1051 , G11C7/12
摘要： A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.
摘要翻译： 半导体读出电路通过使用为每条数据线提供的读出放大器来比较电位与公共参考数据线的电位，来读出多条数据线中的每一条线的电位。 该半导体读出电路具有为每条数据线设置的电流控制电路。 电流控制电路控制对应的一条数据线的电位，使得相应的数据线的电位与参考数据线的电位之间的电位差可以基于关于由 读出放大器。
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公开(公告)号：US20090046514A1
公开(公告)日：2009-02-19
申请号：US12094379
申请日：2006-11-01
申请人： Kaoru Yamamoto , Nobuhiko Ito , Naoki Ueda , Yoshimitsu Yamauchi
发明人： Kaoru Yamamoto , Nobuhiko Ito , Naoki Ueda , Yoshimitsu Yamauchi
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/24 , G11C16/26
摘要： A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.
摘要翻译： 虚拟接地型半导体存储器件包括：存储单元阵列，其中包括第一电极，一对第二电极和电荷保持部分的非易失性存储单元排列成像矩阵的行和列方向; 读取电路，用于选择连接到要读取的所选择的存储器单元的一对第一和第二位线，将第一和第二读取电压分别施加到所选择的第一和第二位线，并且检测存储单元电流的大小 在读取时流入所选存储单元; 电压施加装置，用于将第二读取电压施加到与第一位线的相对侧上的所选择的第二位线相邻的第二相邻位线; 以及用于短路所选择的第二位线和第二相邻位线的短路装置。
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公开(公告)号：US06438035B1
公开(公告)日：2002-08-20
申请号：US09880114
申请日：2001-06-14
IPC分类号： G11C1606
摘要： There is provided a nonvolatile semiconductor storage device capable of securing sufficient read accuracy without providing superfluous sense time margin when there are variations in temperature and transistor characteristics. This nonvolatile semiconductor storage device includes a reference cell 2 whose threshold value is preparatorily set to a value between a lower limit of a threshold voltage distribution in a state 0 in which nonvolatile memory cells MC00 through MC12 have a high threshold value and an upper limit of a threshold voltage distribution in a state 1 in which the memory cells have a low threshold value. When the characteristics of the nonvolatile memory cells MC00 through MC12 shift due to the influence of a change in temperature or the like, the characteristics of the reference cell 2 shift so as to follow this characteristic shift. The operation timing of a sense amplifier section 8 in read operation is generated by a control circuit, and the timing of the termination of the sense operation from among the operation timing is determined by timing control circuit (delay circuit delay and AND circuits AN0 and AN1) with the termination of the sense of the reference cell 2.
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公开(公告)号：US07057944B2
公开(公告)日：2006-06-06
申请号：US11013119
申请日：2004-12-14
IPC分类号： G11C7/06
CPC分类号： G11C7/1069 , G11C7/062 , G11C7/1051 , G11C7/12
摘要： A semiconductor readout circuit reads out a potential of each of plural data lines by comparing the potential with a potential of a common reference data line, using a sense amplifier provided for each of the data lines. This semiconductor readout circuit has a current control circuit provided for each of the data lines. The current control circuit controls the potential of the corresponding one of the data lines so that a potential difference between the potential of the corresponding data line and the potential of the reference data line can be reduced based on an output as to the potential difference detected by the sense amplifier.
摘要翻译： 半导体读出电路通过使用为每条数据线提供的读出放大器来比较电位与公共参考数据线的电位，来读出多条数据线中的每一条线的电位。 该半导体读出电路具有为每条数据线设置的电流控制电路。 电流控制电路控制对应的一条数据线的电位，使得相应的数据线的电位与参考数据线的电位之间的电位差可以基于关于由 读出放大器。
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公开(公告)号：US20060002175A1
公开(公告)日：2006-01-05
申请号：US11173925
申请日：2005-07-01
IPC分类号： G11C11/24
CPC分类号： G11C16/26 , G11C16/0491 , G11C16/24
摘要： A semiconductor memory device having a virtual ground line type memory array structure includes a readout circuit for selecting a pair of selected bit lines connected to the source and the drain of a memory cell to be read, applying a predetermined voltage to between the paired selected bit lines, and sensing a memory cell current flowing through the memory cell to be read, and a counter potential generation circuit for generating from an intermediate node potential, which is higher than any level of the potential on the selected bit lines and supplied from an intermediate node on a current path for feeding the memory cell current in the readout circuit, a counter potential which varies in the same direction as of the intermediate node potential depending on the memory cell current so that its variation is greater than that of the intermediate node potential, wherein the counter potential is applied to an unselected bit line allocated next to one at a high level of the paired selected bit lines.
摘要翻译： 具有虚拟接地线型存储器阵列结构的半导体存储器件包括读出电路，用于选择连接到要读取的存储单元的源极和漏极的一对选定位线，将预定电压施加在成对选定位之间 并且感测流过待读取的存储单元的存储单元电流，以及用于从中间节点电位产生的逆电位产生电路，该中间节点电位高于所选位线上的电位的任何电平，并从中间层 在电流路径上用于馈送读出电路中的存储单元电流的一个节点，根据存储单元电流使与中间节点电位相同的方向变化的反电位，使得其变化大于中间节点电位的变化 ，其中所述计数器电位被施加到在所选择的所述配对的高电平处的一个旁边分配的未选位线 位线。
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公开(公告)号：US06643175B2
公开(公告)日：2003-11-04
申请号：US10320471
申请日：2002-12-17
申请人： Yoshimitsu Yamauchi , Nobuhiko Ito
发明人： Yoshimitsu Yamauchi , Nobuhiko Ito
IPC分类号： G11C1604
CPC分类号： G11C16/3454
摘要： A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
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公开(公告)号：US06512692B2
公开(公告)日：2003-01-28
申请号：US09875142
申请日：2001-06-07
申请人： Yoshimitsu Yamauchi , Nobuhiko Ito
发明人： Yoshimitsu Yamauchi , Nobuhiko Ito
IPC分类号： G11C1604
CPC分类号： G11C16/3454
摘要： A control signal MBPRG is inputted to individual block decoders that constitute a block decoder section. 37 of an ACT type flash memory. Then, the level of the control signal MBPRG is set to “H” to select all the blocks regardless of the contents of address signals a5 through a13, and one word line WL is selected from all the blocks by the addresses a0 through a4. By thus selecting one word line WL every block that is electrically separated by the select transistor and simultaneously applying a write voltage during the test to the same number of word lines WL as the number of blocks, the possible occurrence of a bad influence exerted on the other memory cells is prevented even when the memory cells in which a write operation during the test has been executed include a memory cell that has a negative threshold voltage.
摘要翻译： 控制信号MBPRG被输入到构成块解码器部分的各个块解码器。 37是ACT型闪存。 然后，无论地址信号a5至a13的内容如何，控制信号MBPRG的电平被设置为“H”以选择所有的块，并且通过地址a0至a4从所有的块中选择一个字线WL。 通过这样选择一个字线WL，每个由选择晶体管电隔离的块，并且在测试期间同时向相同数量的字线WL施加一个写入电压作为块的数量，则可能发生不利影响 即使执行了测试期间的写入操作的存储单元，也可以防止其他存储单元包括具有负阈值电压的存储单元。
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公开(公告)号：US07283391B2
公开(公告)日：2007-10-16
申请号：US10934212
申请日：2004-09-03
申请人： Naoki Ueda , Nobuhiko Ito , Yoshimitsu Yamauchi
发明人： Naoki Ueda , Nobuhiko Ito , Yoshimitsu Yamauchi
CPC分类号： G11C16/24
摘要： A semiconductor memory device comprises: a plurality of memory elements; at least one bit line, wherein a memory operation is performed via at least a portion of the bit line with respect to at least one of the plurality of memory elements; and a load resistance regulating circuit for changing a resistance value to reduce or eliminate a difference in bit line load resistance depending on a position of the memory element.
摘要翻译： 半导体存储器件包括：多个存储元件; 至少一个位线，其中通过所述位线的至少一部分相对于所述多个存储器元件中的至少一个执行存储器操作; 以及负载电阻调节电路，用于根据存储元件的位置改变电阻值以减少或消除位线负载电阻的差异。
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