公开(公告)号：US20090201274A1

公开(公告)日：2009-08-13

申请号：US11664084

申请日：2005-09-28

申请人： Nobuhiro Kuwabara ,  Tomoyuki Nagai ,  Tamotsu Sakai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

发明人： Nobuhiro Kuwabara ,  Tomoyuki Nagai ,  Tamotsu Sakai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

IPC分类号： G09G5/00

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2330/021

摘要： A timing signal generating device for a matrix-type display apparatus is disclosed, conducive to reduction of power consumption, the matrix-type display apparatus including the timing signal generating device, and a driving method thereof. In at least one embodiment, a timing signal generating apparatus provided in an active-matrix liquid crystal display apparatus includes a horizontal direction counter and a vertical direction counter for counting a clock number; and a horizontal counter cessation circuit and a vertical counter cessation circuit for stopping the horizontal direction counter and the vertical direction counter at a predetermined timing. With this structure, at least one embodiment of the present invention achieves reduction in power consumption in the liquid crystal display apparatus.

摘要翻译： 公开了一种用于矩阵型显示装置的定时信号产生装置，有助于降低功耗，包括定时信号产生装置的矩阵型显示装置及其驱动方法。 在至少一个实施例中，设置在有源矩阵液晶显示装置中的定时信号发生装置包括水平方向计数器和用于对时钟数进行计数的垂直方向计数器; 以及用于在预定定时停止水平方向计数器和垂直方向计数器的水平计数器停止电路和垂直计数器停止电路。 利用这种结构，本发明的至少一个实施例实现了液晶显示装置的功耗的降低。

公开(公告)号：US20110181556A1

公开(公告)日：2011-07-28

申请号：US11665332

申请日：2005-09-09

申请人： Tamotsu Sakai ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

发明人： Tamotsu Sakai ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

IPC分类号： G06F3/038 ,  H03M9/00

CPC分类号： G09G3/3685 ,  G09G2330/021

摘要： The present invention relates to a serial-parallel conversion circuit of a display device.First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.

摘要翻译： 本发明涉及一种显示装置的串并转换电路。 与移位寄存器（31）的各级相关联地提供用于根据从移位寄存器（31）输出的采样脉冲采样和锁存串行信号的第一锁存电路。 此外，用于锁存从第一锁存电路输出的信号的第二锁存电路与移位寄存器（31）的各个级的部分相关联地被提供。 在这种情况下，在移位寄存器（31）的所有阶段中，与第二锁存电路相关联的级数小于移位寄存器的总数量两个或更多。

公开(公告)号：US20090051678A1

公开(公告)日：2009-02-26

申请号：US11887783

申请日：2006-04-03

申请人： Masakazu Satoh ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Tamotsu Sakai ,  Shuji Nishi

发明人： Masakazu Satoh ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Tamotsu Sakai ,  Shuji Nishi

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/2092 ,  G09G3/3696 ,  G09G2310/0289

摘要： A readily-mountable low-cost active matrix display apparatus with a setup function is provided. A serial interface circuit 20 and setup circuits 16 are each formed of TFT elements on a liquid crystal panel 11. The serial interface circuit 20 performs serial-parallel conversion on a setup control signal 17 serially inputted via setup terminals 15. The setup circuits 16 change the states of signals flowing in the liquid crystal panel 11 in accordance with signals outputted in parallel from the serial interface circuit 20. Thus, it is possible to change the potential, timing, etc., of signals inputted to or outputted from any peripheral circuits formed on the liquid crystal panel 11 or any peripheral circuits included in a semiconductor chip mounted on the surface of the liquid crystal panel 11.

摘要翻译： 提供了具有设置功能的易于安装的低成本有源矩阵显示装置。 串行接口电路20和设置电路16各自由液晶面板11上的TFT元件形成。串行接口电路20对通过设置端子15串行输入的设置控制信号17进行串行 - 并行转换。设置电路16改变 根据从串行接口电路20并行输出的信号在液晶面板11中流动的信号的状态。因此，可以改变输入到或从任何外围电路输出的信号的电位，定时等 形成在液晶面板11上或包含在安装在液晶面板11的表面上的半导体芯片中的任何外围电路。

公开(公告)号：US08094116B2

公开(公告)日：2012-01-10

申请号：US11665332

申请日：2005-09-09

申请人： Tamotsu Sakai ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

发明人： Tamotsu Sakai ,  Tomoyuki Nagai ,  Kazuhiro Maeda ,  Shuji Nishi ,  Masakazu Satoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G2330/021

摘要： The present invention relates to a serial-parallel conversion circuit of a display device.First latch circuits for sampling and latching a serial signal in accordance with sampling pulses outputted from a shift register (31) are provided in association with stages of the shift register (31). In addition, second latch circuits for latching signals outputted from the first latch circuits are provided in association with portions of the stages of the shift register (31). In this case, of all the stages of the shift register (31), the number of stages associated with the second latch circuits is less than the total number of stages of the shift register by two or more.

摘要翻译： 本发明涉及一种显示装置的串并转换电路。 与移位寄存器（31）的各级相关联地提供用于根据从移位寄存器（31）输出的采样脉冲采样和锁存串行信号的第一锁存电路。 此外，用于锁存从第一锁存电路输出的信号的第二锁存电路与移位寄存器（31）的各个级的部分相关联地被提供。 在这种情况下，在移位寄存器（31）的所有阶段中，与第二锁存电路相关联的级数小于移位寄存器的总数量两个或更多个。

公开(公告)号：US20120154354A1

公开(公告)日：2012-06-21

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/02 ,  G01J1/46

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US08780101B2

公开(公告)日：2014-07-15

申请号：US13391654

申请日：2010-07-12

申请人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

发明人： Sachio Tsujino ,  Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiroh Shiraki ,  Hiroaki Sugiyama ,  Nobuhiro Kuwabara

IPC分类号： G09G5/00

CPC分类号： H01L27/14643 ,  G06F3/0412 ,  G06F3/042 ,  H04N5/357

摘要： By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods. A voltage that keeps the potential of the storage node lower than the threshold value of the MOS transistor (M1) is supplied to the second terminal of the storage capacitor in the reset period and the storage period, and a voltage that thrusts the potential of the storage node (N2) upward to the threshold value of the MOS transistor (M1) or higher is supplied to the second terminal of the storage capacitor in the readout period.

摘要翻译： 通过减少由于馈通而发生的存储节点的潜在下降，存储电容器的电容降低并且传感器灵敏度得到改善。 在光电传感器中，根据存储节点（N2）的电位输出信号的存储电容器（C2）的第一端子和MOS晶体管（M1）的栅极连接到存储节点（N2 ）。 在复位周期中将正向偏置脉冲电压提供给第一光电二极管（DS）的阳极，并且在存储周期和读出周期中向第一光电二极管的阳极提供反向偏置电压。 在所有操作周期中，向第二光电二极管（DM）的阳极提供反向偏置电压。 在复位期间和保存期间，保持存储节点的电位低于MOS晶体管（M1）的阈值的电压被提供给存储电容器的第二端子，并且将电压 存储节点（N2）向上升到MOS晶体管（M1）或更高的阈值，在读出期间提供给存储电容器的第二端。

公开(公告)号：US20100259565A1

公开(公告)日：2010-10-14

申请号：US12733884

申请日：2008-06-19

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

IPC分类号： G09G5/10

CPC分类号： G09G3/20 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13606 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021 ,  H01L27/124

摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

公开(公告)号：US08305315B2

公开(公告)日：2012-11-06

申请号：US12733884

申请日：2008-06-19

申请人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

发明人： Yousuke Nakagawa ,  Kazuhiro Maeda ,  Ichiro Shiraki ,  Shuji Nishi ,  Sachio Tsujino

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G02F1/13454 ,  G02F1/1368 ,  G02F2001/13606 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0297 ,  G09G2330/021 ,  H01L27/124

摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。

公开(公告)号：US20090174372A1

公开(公告)日：2009-07-09

申请号：US12226131

申请日：2007-02-13

申请人： Kazuhiro Maeda ,  Ichiro Shiraki ,  Shinsaku Shimizu ,  Shuji Nishi

发明人： Kazuhiro Maeda ,  Ichiro Shiraki ,  Shinsaku Shimizu ,  Shuji Nishi

IPC分类号： H02J7/00 ,  H02J3/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2310/0248 ,  G09G2310/0272 ,  G09G2320/0252 ,  Y10T307/50

摘要： In one embodiment of the present invention, a voltage source is disclosed including a lower output impedance is connected to a capacitive load via a switch element and a voltage source including a higher output impedance is connected to the capacitive load via a switch element. Until a potential of an output terminal attains a reference potential, a comparator keeps the switch element in an ON state so that the voltage source writes a potential onto the capacitive load. When the potential of the output terminal exceeds the reference potential, the comparator causes the switch element to be in an ON state so that the voltage source writes a potential onto the capacitive load so as to have a predetermined potential.

摘要翻译： 在本发明的一个实施例中，公开了一种电压源，其包括经由开关元件连接到电容性负载的较低输出阻抗，并且包括较高输出阻抗的电压源经由开关元件连接到电容性负载。 直到输出端子的电位达到参考电位，比较器将开关元件保持在导通状态，使得电压源将电位写入电容性负载。 当输出端子的电位超过参考电位时，比较器使开关元件处于导通状态，使得电压源将电位写入电容性负载以具有预定电位。

公开(公告)号：US07711526B2

公开(公告)日：2010-05-04

申请号：US10891083

申请日：2004-07-15

申请人： Kazuhiro Maeda ,  Tamotsu Sakai ,  Yasushi Kubota ,  Shigeki Imai ,  Kenshi Tada ,  Kenji Taniguchi

发明人： Kazuhiro Maeda ,  Tamotsu Sakai ,  Yasushi Kubota ,  Shigeki Imai ,  Kenshi Tada ,  Kenji Taniguchi

IPC分类号： G06F7/60 ,  G06G7/62

CPC分类号： G06F17/5036

摘要： A transistor model for a simulator simulates a resistance between a source region and a drain region with a model equation which has terms representing resistance values corresponding respectively to areas of mutually different impurity concentrations below a gate section in simulating characteristics of a transistor. At least two of the terms each having a threshold parameter indicating a voltage at which a semiconductor element composed of the associated region and regions adjacent to that region changes from an ON state to an OFF state. The threshold parameters of the terms being specified independently from each other. Thus, the characteristics of a transistor having a set of areas of mutually different impurity concentrations below a gate section, inclusive of subthreshold regions which are difficult to evaluate through actual measurement, can be simulated to high accuracy while preserving a good fit with a capacitance model.

摘要翻译： 用于模拟器的晶体管模型利用模拟方程来模拟源极区域和漏极区域之间的电阻，其模型方程具有表示在模拟晶体管的特性中分别对应于栅极部分的相互不同的杂质浓度的区域的电阻值的项。 每个术语中的至少两个术语具有表示由相关区域和与该区域相邻的区域组成的半导体元件的电压的阈值参数从ON状态变为OFF状态。 术语的阈值参数彼此独立地指定。 因此，通过实际测量难以评估的具有低于栅极部分的杂质浓度相互不同的杂质浓度的区域的集合的特性可以被模拟成高精度，同时保持与电容模型的良好匹配 。