公开(公告)号：US5438211A

公开(公告)日：1995-08-01

申请号：US220708

申请日：1994-03-31

申请人： Nobuo Nakamura ,  Yoshiyuki Matsunaga ,  Yoshihito Koya ,  Yukio Endo

发明人： Nobuo Nakamura ,  Yoshiyuki Matsunaga ,  Yoshihito Koya ,  Yukio Endo

IPC分类号： H01L29/768 ,  H01L29/78

CPC分类号： H01L29/76816 ,  H01L29/76841

摘要： A charge-transfer device contains a high-resistance p-well layer formed in the surface of an n-type semiconductor substrate. In the surface of the well layer, a charge-transfer n-channel layer, a charge storage n-channel layer, a charge release n-channel layer, and a charge release n-type drain are formed continuously. An output gate electrode is provided above the junction of the transfer channel layer and the storage channel layer, with an insulating film interposed therebetween. Provided above the release channel layer is a reset gate electrode with an insulating film interposed therebetween. In the surface of the storage channel layer, a charge-sensing p-channel layer of a charge-sensing transistor is formed. The charge-sensing channel layer is arranged so as to be in contact with neither the transfer channel layer nor the release channel layer. The storage channel layer is arranged so as to contain a first surface portion which adjoins the transfer channel layer and is in contact with a covering insulating film, and a second surface portion which adjoins the release channel layer and is in contact with the covering insulating film. In the surface of the substrate, a p-type source and drain layers of the charge-sensing transistor are formed so as to face each other with the sensing channel interposed therebetween. The potential of the storage channel layer without charges is set higher than that of the release drain layer.

摘要翻译： 电荷转移装置包含在n型半导体衬底的表面上形成的高电阻p阱层。 在阱层的表面中连续地形成电荷传输n沟道层，电荷存储n沟道层，电荷释放n沟道层和电荷释放型n型漏极。 输出栅电极设置在传输沟道层和存储沟道层的结的上方，隔着绝缘膜。 在释放通道层上方设置有复位栅电极，其间具有绝缘膜。 在存储通道层的表面形成电荷感测晶体管的电荷感应p沟道层。 电荷感测沟道层被布置成与传输沟道层和释放通道层都不接触。 存储通道层被布置成包含邻接传输沟道层并与覆盖绝缘膜接触的第一表面部分和与释放通道层相邻并与覆盖绝缘膜接触的第二表面部分 。 在基板的表面中，电荷感测晶体管的p型源极和漏极层形成为彼此面对，并且其间插入感测通道。 没有电荷的存储通道层的电位被设定为高于释放漏极层的电位。

公开(公告)号：US08310872B2

公开(公告)日：2012-11-13

申请号：US12863409

申请日：2009-01-16

申请人： Yoshihito Koya ,  Gary B. Bronner ,  Frederick A. Ware

发明人： Yoshihito Koya ,  Gary B. Bronner ,  Frederick A. Ware

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/24

摘要： A NAND flash memory device having a bit line and a plurality of storage cells coupled thereto. Programming circuitry is coupled to the plurality of storage cells concurrently to program two or more of the storage cells in different NAND strings associated with the same bit line.

摘要翻译： 具有位线和与其耦合的多个存储单元的NAND快闪存储器件。 编程电路同时耦合到多个存储单元，以对与相同位线相关联的不同NAND串中的两个或更多个存储单元进行编程。

公开(公告)号：US08773925B2

公开(公告)日：2014-07-08

申请号：US13578498

申请日：2010-12-01

申请人： Yoshihito Koya ,  Brent Haukness

发明人： Yoshihito Koya ,  Brent Haukness

IPC分类号： G11C7/10

CPC分类号： G11C7/16 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/565 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/005 ,  G11C2207/2254

摘要： A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.

摘要翻译： 多级动态随机存取存储器（MLDRAM）使用存储在单个存储器单元中的单元电压来表示多于一位的原始位组合。 电池电压是多个离散的模拟电压范围之一，每个对应于位组合的可能值的相应一个。 在读取所选存储单元时，存储的电荷通过本地位线被传送到前置放大器。 前置放大器放大本地位线上的信号，并用表示存储电压的模拟信号驱动全局位线。 数字转换器将全局位线上的模拟信号转换为读位组合。 读取位组合然后通过全局位线移动到数据高速缓存。 数据高速缓存将模拟电压写入存储单元以写入新值或恢复在读取单元格时销毁的数据。

公开(公告)号：US20100214822A1

公开(公告)日：2010-08-26

申请号：US12680986

申请日：2008-07-22

申请人： Frederick A. Ware ,  Yoshihito Koya

发明人： Frederick A. Ware ,  Yoshihito Koya

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： G11C11/4076 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/2227

摘要： This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.

摘要翻译： 本公开描述了一种用于从集成电路装置内的至少一个存储单元的电容性能量存储装置从初始电压充电到最终电压的系统，其中集成电路装置包括多个存储单元，其至少形成在 部分由电容式储能装置。 在操作期间，系统通过使用一个或多个电压源将电容性储能装置从初始电压逐步地通过一个或多个逐渐升高的中间电压电平逐步充电。 具体地，每个中间电压电平在初始电压和最终电压之间，并且每个电压源产生相应的中间电压电平。 注意，通过一个或多个中间电压电容对电容性储能装置充电可减少充电过程中的能量耗散。

公开(公告)号：US20190066762A1

公开(公告)日：2019-02-28

申请号：US16112133

申请日：2018-08-24

申请人： Yoshihito Koya

发明人： Yoshihito Koya

IPC分类号： G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  H01L27/108 ,  G11C11/4096

摘要： Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar that has a length extending in a direction perpendicular to a substrate of a memory device. Each of the volatile memory cells includes a capacitor and at least one transistor. The capacitor includes a capacitor plate. The capacitor plate is either formed from a portion a semiconductor material of the pillar or formed from a conductive material separated from the pillar by a dielectric.

公开(公告)号：US08441872B2

公开(公告)日：2013-05-14

申请号：US13552511

申请日：2012-07-18

申请人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

发明人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

IPC分类号： G11C7/00

CPC分类号： G06F13/4239 ,  G11C5/02 ,  G11C5/04 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/10159 ,  Y02P70/611

摘要： A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate a first data transfer between the memory controller and a first memory device, and generating a strobe signal to accompany data associated with the first data transfer. In the second mode, the controller is configured to operate by issuing a memory access command to initiate a second data transfer between the memory controller and at least first and second memory devices involving a full width that includes data widths of both the first and second memory devices, and issuing first and second strobe signals that accompany respective data transfers associated with each of the data widths of the first and second memory devices.

摘要翻译： 公开了一种在存储器控制器中的操作方法，包括生成模式控制信号以指定第一和第二模式中的至少一个。 在第一模式中，存储器控制器被配置为通过发出存储器访问命令来操作，以启动存储器控制器和第一存储器件之间的第一数据传输，并且产生选通信号以伴随与第一数据传输相关联的数据。 在第二模式中，控制器被配置为通过发出存储器访问命令来进行操作，以在存储器控制器与包括全宽度的至少第一和第二存储器件之间的第二数据传输中包括第一和第二存储器的数据宽度 并且发出伴随与第一和第二存储器设备的每个数据宽度相关联的相应数据传输的第一和第二选通信号。

公开(公告)号：US20120314484A1

公开(公告)日：2012-12-13

申请号：US13578498

申请日：2010-12-01

申请人： Yoshihito Koya ,  Brent Haukness

发明人： Yoshihito Koya ,  Brent Haukness

IPC分类号： G11C7/00 ,  G11C11/24

CPC分类号： G11C7/16 ,  G11C11/401 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/565 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/005 ,  G11C2207/2254

摘要： A multi-level dynamic random-access memory (MLDRAM) represents an original bit combination of more than one bit using a cell voltage stored in a single memory cell. The cell voltage is in one of a number of discrete analog voltage ranges each corresponding to a respective one of the possible values of the bit combination. In reading a selected memory cell, stored charge is conveyed via a local bitline to a preamplifier. The preamplifier amplifies the signal on the local bitline and drives a global bitline with an analog signal representative of the stored voltage. A digitizer converts the analog signal on the global bitline into a read bit combination. The read bit combination is then moved to a data cache over the global bitline. The data cache writes an analog voltage back to the memory cell to write a new value or restore data destroyed in reading the cell.

摘要翻译： 多级动态随机存取存储器（MLDRAM）使用存储在单个存储器单元中的单元电压来表示多于一位的原始位组合。 电池电压是多个离散的模拟电压范围之一，每个对应于位组合的可能值的相应一个。 在读取所选存储单元时，存储的电荷通过本地位线被传送到前置放大器。 前置放大器放大本地位线上的信号，并用表示存储电压的模拟信号驱动全局位线。 数字转换器将全局位线上的模拟信号转换为读位组合。 读取位组合然后通过全局位线移动到数据高速缓存。 数据高速缓存将模拟电压写入存储单元以写入新值或恢复在读取单元格时销毁的数据。

公开(公告)号：US06700572B1

公开(公告)日：2004-03-02

申请号：US09565607

申请日：2000-05-04

申请人： Yoshihito Koya

发明人： Yoshihito Koya

IPC分类号： G06T1500

CPC分类号： H04N13/139 ,  H04N13/31

摘要： A three-dimensional display is provided that simplifies the display system and reduces hardware costs by using a predetermined mask unit positioned before the display screen of a CRT displaying an image. The three-dimensional display includes a synthesis unit, display unit, and mask plate. The shift circuit of the synthesis unit shifts the images of the perspective cameras from the image of the reference camera, while the mapping circuit combines the reference image and the shifted images of the cameras. Further, the filter circuit removes unnecessary pixels from the synthesized image, then the sync signal insertion circuit inserts a horizontal sync signal and vertical sync signal to produce a synthesized image. This synthesized image is displayed on the CRT display screen of the display unit. Light from the images captured by the cameras is focused at the viewing perspectives P1, P2, and P3 by the holes of the mask unit.

摘要翻译： 提供一种三维显示器，其通过使用位于显示图像的CRT的显示屏幕之前的预定掩模单元来简化显示系统并降低硬件成本。 三维显示器包括合成单元，显示单元和掩模板。 合成单元的移位电路从参考摄像机的图像移位透视摄像机的图像，而映射电路组合参考图像和照相机的偏移图像。 此外，滤波器电路从合成图像中去除不必要的像素，然后同步信号插入电路插入水平同步信号和垂直同步信号以产生合成图像。 该合成图像显示在显示单元的CRT显示屏上。 由摄像机拍摄的图像的光通过掩模单元的孔聚焦于观看透视P1，P2和P3。

公开(公告)号：US08243484B2

公开(公告)日：2012-08-14

申请号：US12532914

申请日：2008-03-27

申请人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

发明人： Jade M. Kizer ,  Yoshihito Koya ,  Frederick A. Ware

IPC分类号： G11C5/02

CPC分类号： G06F13/4239 ,  G11C5/02 ,  G11C5/04 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/10159 ,  Y02P70/611

摘要： A memory system comprises a circuit board 40 including N data signal lines 60, 65 and at least two strobe signal lines 70, 75, and first and second memory devices 50, 55 secured to opposing surfaces 40a, 40b of the circuit board. Each memory device is coupled to a portion of the N data signal lines and to a portion of the at least two strobe signal lines such that the devices do not share any of the N data signal lines and such that the devices do not share any of the strobe signal lines. The memory system further includes a controller 45 to communicate in parallel with the first and second memory devices through the N data signal lines and the at least two strobe signal lines.

摘要翻译： 存储器系统包括电路板40，其包括N条数据信号线60,65和至少两个选通信号线70,75以及固定到电路板的相对表面40a，40b的第一和第二存储器件50,55。 每个存储器件耦合到N个数据信号线的一部分和至少两个选通信号线的一部分，使得器件不共享N个数据信号线中的任何一个，并且使得器件不共享 选通信号线。 存储系统还包括控制器45，通过N个数据信号线和至少两个选通信号线与第一和第二存储器装置并行通信。

公开(公告)号：US08174923B2

公开(公告)日：2012-05-08

申请号：US12680986

申请日：2008-07-22

申请人： Frederick A. Ware ,  Yoshihito Koya

发明人： Frederick A. Ware ,  Yoshihito Koya

IPC分类号： G11C5/14 ,  G11C11/24

CPC分类号： G11C11/4076 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/2227

摘要： This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.

摘要翻译： 本公开描述了一种用于从集成电路装置内的至少一个存储单元的电容性能量存储装置从初始电压充电到最终电压的系统，其中集成电路装置包括多个存储单元，其至少形成在 部分由电容式储能装置。 在操作期间，系统通过使用一个或多个电压源将电容性储能装置从初始电压逐步地通过一个或多个逐渐升高的中间电压电平逐步充电。 具体地，每个中间电压电平在初始电压和最终电压之间，并且每个电压源产生相应的中间电压电平。 注意，通过一个或多个中间电压电容对电容性储能装置充电可减少充电过程中的能量耗散。