-
公开(公告)号：US20200014377A1
公开(公告)日：2020-01-09
申请号：US16486460
申请日：2018-02-15
发明人： Bard HAAHEIM , Ola BRUSET
摘要： A duty cycle conversion circuit portion comprises N inverters, wherein N is an integer greater than two. The duty cycle conversion circuit is arranged to receive N input signals each having a duty cycle between 1/N and 2/N. Each of the N input signals is applied to a respective input terminal of one of the N inverters such that each inverter receives a different input signal. Each of the N input signals is applied to a respective power terminal of one of the N inverters such that each inverter is powered by a different input signal. Each inverter receives different input signal at its respective input terminal to the input signal applied to its respective power terminal.
-
公开(公告)号：US20200088767A1
公开(公告)日：2020-03-19
申请号：US16472582
申请日：2017-12-20
发明人： Lukasz FARIAN , Ola BRUSET , Werner LUZI
摘要： A voltage divider circuit comprises: a resistive divider circuit portion comprising at least first and second resistors (R1, R2), wherein said first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node therebetween; a capacitive divider circuit portion comprising at least first and second capacitors (C1, C2), wherein said first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node therebetween; and a switching circuit portion arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider circuit portion is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider circuit portion is disabled and the output node is not connected to the refresh node.
-
公开(公告)号：US20170346473A1
公开(公告)日：2017-11-30
申请号：US15536246
申请日：2015-12-14
发明人： Ola BRUSET , Phil CORBISHLEY
CPC分类号： H03K5/2481 , H03G3/3036 , H04B1/16
摘要： A differential comparator has a first input and a second input comprises: first and second transistors arranged as a differential pair connected to the first and second inputs respectively; and a constant current arrangement disposed between said differential pair and a first supply rail; wherein a first path between the first transistor and the constant current arrangement has a different resistance to a second path between the second transistor and the constant current arrangement. Also disclosed is a radio receiver employing such a differential comparator.
-
公开(公告)号：US20240291700A1
公开(公告)日：2024-08-29
申请号：US18568492
申请日：2022-06-09
发明人： Ola BRUSET
CPC分类号： H04L27/12 , H04L27/16 , H04W52/0235
摘要： According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.
-
公开(公告)号：US20240283459A1
公开(公告)日：2024-08-22
申请号：US18569459
申请日：2022-06-13
发明人： Carsten WULFF , Tor Øyvind VEDAL , Ola BRUSET , Shankkar BALASUBRAMANIAN , Ruben UNDHEIM , Harald GARVIK
CPC分类号： H03L7/104 , H03L7/093 , H03L7/099 , H03L2207/50
摘要： According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.
-
-
-
-
搜索结果
5 条记录 (耗时 0.015 秒)
