公开(公告)号：US08693278B2

公开(公告)日：2014-04-08

申请号：US13414152

申请日：2012-03-07

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C8/00 ,  G11C8/10 ,  G11C16/24

CPC classification number: G11C11/4063 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/24

Abstract: Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines.

Abstract translation: 本文公开了一种半导体器件，其包括本地位线，全局位线，本地开关控制线，主开关控制线，响应于本地开关控制的电位而控制局部位线和全局位线之间的电连接的分层开关 线路，本地开关驱动器响应于主开关控制线的电位而驱动本地开关控制线，并且主开关驱动器选择性地激活主开关控制线。

公开(公告)号：US20070076495A1

公开(公告)日：2007-04-05

申请号：US11633570

申请日：2006-12-05

Applicant: Noriaki Mochida ,  Chiaki Dono ,  Tomohiko Sato

Inventor： Noriaki Mochida ,  Chiaki Dono ,  Tomohiko Sato

IPC: G11C29/00

CPC classification number: G11C29/06 ,  G11C11/401 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/1204

Abstract: A wafer-level burn-in test for a write operation to memory cells is disclosed. The memory cells are associated with a column switch transistor having a gate. In accordance with the method, a voltage level supplied for the gate is changed in correspondence with a level written into the memory cells. When a stress voltage is written into the memory cells, the gate of the column switch transistor is applied with a high level voltage, ex. a voltage higher than a normal VDD. When a zero voltage is written into the memory cells, the gate of the column switch transistor is applied with a low level voltage, ex. a zero voltage or a negative voltage.

Abstract translation: 公开了用于对存储器单元进行写操作的晶片级老化测试。 存储单元与具有栅极的列开关晶体管相关联。 根据该方法，与写入存储单元的电平相对应地改变为栅极提供的电压电平。 当应力电压被写入存储单元时，列开关晶体管的栅极被施加高电平电压，例如。 电压高于正常VDD。 当零电压被写入存储单元时，列开关晶体管的栅极被施加低电平电压，例如。 零电压或负电压。

公开(公告)号：US07193915B2

公开(公告)日：2007-03-20

申请号：US10933290

申请日：2004-09-03

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C7/02 ,  G11C7/10 ,  G11C8/00 ,  G11C11/06

CPC classification number: G11C7/1096 ,  G11C7/1078 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2207/2227

Abstract: When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corresponding to the command.

Abstract translation: 当向半导体存储器件输入命令时，将子阈值电流减小到与该命令对应的预定值。 在子阈值电流的减小完成之后，半导体存储器件根据该命令开始运行。

公开(公告)号：US20100149894A1

公开(公告)日：2010-06-17

申请号：US12654202

申请日：2009-12-14

Applicant: Noriaki Mochida ,  Kyoichi Nagata

Inventor： Noriaki Mochida ,  Kyoichi Nagata

IPC: G11C29/00 ,  G11C7/06 ,  G11C8/00

CPC classification number: G11C11/4076 ,  G11C11/4091 ,  G11C29/84

Abstract: To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.

Abstract translation: 为了构成存储单元阵列，设置在存储单元阵列的外部并放大从存储单元阵列读出的数据的读取放大器，设置在存储单元阵列外部的写放大器，并放大要写入存储单元阵列的数据 以及设置在存储单元阵列外部并经由开关连接到读取放大器的输入端子和写入放大器的输出端子的释放存储单元。 利用这种配置，根据存储块的位置，不需要改变操作主放大器和浮雕存储单元的定时。 此外，可以使连接到浮雕存储单元所需的部件的数量最小化。

公开(公告)号：US07180817B2

公开(公告)日：2007-02-20

申请号：US11262801

申请日：2005-11-01

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C8/00

CPC classification number: G11C11/4097 ,  G11C2207/002

Abstract: A semiconductor memory device has column selecting switches in a hierarchical structure. A plurality of local column selecting switches for controlling connections between bit lines and local I/O lines. A global column selecting switch connects column selecting lines and four local column selecting switches when a bit precharging signal becomes low in level for stopping precharging the bit lines. As the column selecting switches are in a hierarchical structure including the global column selecting switch that is directly controlled by the column selecting lines and the local column selecting switches that are controlled by the global column selecting switch, a load on the column selecting lines is reduced for high-speed operation. Even when bit lines are divided into a greater number of bit lines, the number of column selecting switches that are energized by a single column selecting line is not increased, and a signal delay is prevented from occurring.

Abstract translation: 半导体存储器件具有分级结构的列选择开关。 多个本地列选择开关，用于控制位线和本地I / O线之间的连接。 当位预充电信号变为低电平以停止预充电位线时，全局列选择开关连接列选择线和四个本地列选择开关。 由于列选择开关是分层结构，包括由列选择线直接控制的全局列选择开关和由全局列选择开关控制的本地列选择开关，列选择线的负载减小 用于高速运行。 即使当位线被分成更大数量的位线时，由单个列选择线激励的列选择开关的数量也不会增加，并且防止发生信号延迟。

公开(公告)号：US20050052909A1

公开(公告)日：2005-03-10

申请号：US10933290

申请日：2004-09-03

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4097 ,  G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/1078 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2207/2227

Abstract: When a command is input to a semiconductor memory device, a sub-threshold current is reduced to a predetermined value corresponding to the command. After the reduction of the sub-threshold current is completed, the semiconductor memory device starts to operate corresponding to the command.

Abstract translation: 当向半导体存储器件输入命令时，将子阈值电流减小到与该命令对应的预定值。 在子阈值电流的减小完成之后，半导体存储器件开始对应于该命令的操作。

公开(公告)号：US20120120747A1

公开(公告)日：2012-05-17

申请号：US13276919

申请日：2011-10-19

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C7/06

CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/08 ,  G11C7/22 ,  G11C8/12

Abstract: A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.

Abstract translation: 第一数据放大器连接到由X地址信号和通过预编码Y地址信号获得的选择信号所标识的第一存储器单元。 第二数据放大器连接到由X地址信号识别的第二存储器单元和通过延迟选择信号而获得的延迟选择信号。 发生器通过延迟第一数据放大器的操作时钟信号来产生延迟的操作时钟信号。 定时控制器接收用于控制第一数据放大器的操作的第一控制信号和用于控制第二数据放大器的操作的第二控制信号，在根据操作时钟的定时将第一控制信号输出到第一数据放大器 信号，并根据延迟的操作时钟信号在定时输出第二控制信号到第二数据放大器。

公开(公告)号：US08649233B2

公开(公告)日：2014-02-11

申请号：US13276919

申请日：2011-10-19

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C7/22 ,  G11C8/18

CPC classification number: G11C7/18 ,  G11C5/025 ,  G11C7/08 ,  G11C7/22 ,  G11C8/12

Abstract: A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal.

Abstract translation: 第一数据放大器连接到由X地址信号和通过预编码Y地址信号获得的选择信号所标识的第一存储器单元。 第二数据放大器连接到由X地址信号识别的第二存储器单元和通过延迟选择信号而获得的延迟选择信号。 发生器通过延迟第一数据放大器的操作时钟信号来产生延迟的操作时钟信号。 定时控制器接收用于控制第一数据放大器的操作的第一控制信号和用于控制第二数据放大器的操作的第二控制信号，在根据操作时钟的定时将第一控制信号输出到第一数据放大器 信号，并根据延迟的操作时钟信号在定时输出第二控制信号到第二数据放大器。

公开(公告)号：US08233344B2

公开(公告)日：2012-07-31

申请号：US12783918

申请日：2010-05-20

Applicant: Noriaki Mochida

Inventor： Noriaki Mochida

IPC: G11C7/00

CPC classification number: G11C7/1039 ,  G11C7/1051 ,  G11C7/1069 ,  G11C8/12 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C2207/002

Abstract: A semiconductor device includes a plural number of sense amplifiers that sense at least two data in parallel and that operate under a first frequency, and a multiplexer that operates under a second frequency higher than the first frequency and that sequentially serially outputs the data sensed in parallel. The semiconductor device also includes a driver circuit having a latch circuit connected to an output of the multiplexer, and an output driver circuit connected to the latch circuit and operating under the second frequency. The voltage of a power supply of the sense amplifiers is the same as the voltage of a power supply of the output driver circuit. The power supply of the sense amplifiers and the power supply of the output driver circuit are connected to respective different power supply lines.

Abstract translation: 一种半导体器件包括多个并行感测至少两个数据并在第一频率下操作的读出放大器，以及在比第一频率高的第二频率下工作的多路复用器，并且顺序地串行地输出并行感测的数据 。 半导体器件还包括具有连接到多路复用器的输出的锁存电路的驱动电路和连接到锁存电路并在第二频率下工作的输出驱动器电路。 读出放大器的电源的电压与输出驱动器电路的电源的电压相同。 读出放大器的电源和输出驱动器电路的电源连接到各个不同的电源线。

公开(公告)号：US08208324B2

公开(公告)日：2012-06-26

申请号：US12654202

申请日：2009-12-14

Applicant: Noriaki Mochida ,  Kyoichi Nagata

Inventor： Noriaki Mochida ,  Kyoichi Nagata

IPC: G11C29/00 ,  G11C7/06 ,  G11C8/00

CPC classification number: G11C11/4076 ,  G11C11/4091 ,  G11C29/84

Abstract: To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized.

Abstract translation: 为了构成存储单元阵列，设置在存储单元阵列的外部并放大从存储单元阵列读出的数据的读取放大器，设置在存储单元阵列外部的写放大器，并放大要写入存储单元阵列的数据 以及设置在存储单元阵列外部并经由开关连接到读取放大器的输入端子和写入放大器的输出端子的释放存储单元。 利用这种配置，根据存储块的位置，不需要改变操作主放大器和浮雕存储单元的定时。 此外，可以使连接到浮雕存储单元所需的部件的数量最小化。