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公开(公告)号：US07049867B2
公开(公告)日：2006-05-23
申请号：US10915340
申请日：2004-08-11
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/1803
摘要： A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
摘要翻译： 使得压控振荡器在短时间内收敛到稳定状态的PLL电路，并且即使在提供参考输入信号的周期期间发生不连续性，也产生具有高稳定性的时钟信号。 PLL电路具有压控振荡器，用于输出时钟控制，第一计数器由参考输入信号复位，该参考输入信号在用于输出第一信号的预定周期内比参考周期长一个周期;第二计数器，用于输出第二信号 ，用于复位第二计数器的复位脉冲发生电路，用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号比参考值更长的不连续输入检测部分 期。
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公开(公告)号：US20050040872A1
公开(公告)日：2005-02-24
申请号：US10915340
申请日：2004-08-11
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
CPC分类号： H03L7/18 , H03L7/1803
摘要： The present invention provides a PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal. The PLL circuit of the present invention has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.
摘要翻译： 本发明提供一种使电压控制振荡器在短时间内收敛到稳定状态的PLL电路，即使在参考输入信号的周期中发生不连续性，也产生高稳定性的时钟信号。 本发明的PLL电路具有电压控制振荡器，用于输出时钟控制，第一计数器由参考输入信号复位，该参考输入信号在预定周期内具有比参考周期长一个周期，用于输出第一信号;第二计数器， 输出第二信号，用于复位第二计数器的复位脉冲发生电路，用于保持和输出由相位误差信号变化的控制电压的环路滤波器和用于检测在其周期之后最初输入的参考输入信号的不连续输入检测部分 比参考期长。
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公开(公告)号：US20050156812A1
公开(公告)日：2005-07-21
申请号：US10995106
申请日：2004-11-24
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
CPC分类号： G09G5/008 , G06F3/1423 , G09G3/3611
摘要： A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.
摘要翻译： 显示面板控制电路包括用于输出时钟信号的压控振荡器（VCO），第一面板水平系统脉冲产生部分，第二面板水平系统脉冲产生部分，垂直系统脉冲产生部分 第一和第二面板，相位比较器和平滑元件。 第一面板水平系统脉冲产生部分和第二面板水平系统脉冲产生部分分别从信号VCOCLK 1生成第一面板水平系统输出组的参考信号和第二面板水平系统输出组的参考信号 从VCO输出。 因此，可以同时驱动两个不同的面板。
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4.发明授权Control circuit for displaying the same video simultaneously to two or more panels 失效用于将同一视频同时显示到两个或多个面板的控制电路公开(公告)号：US07439936B2
公开(公告)日：2008-10-21
申请号：US10995106
申请日：2004-11-24
申请人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
发明人： Norihide Kinugasa , Yoshio Nirasawa , Hideo Hamaguchi , Sachi Ota
IPC分类号： G09G5/00
CPC分类号： G09G5/008 , G06F3/1423 , G09G3/3611
摘要： A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.
摘要翻译： 显示面板控制电路包括用于输出时钟信号的压控振荡器（VCO），第一面板水平系统脉冲产生部分，第二面板水平系统脉冲产生部分，垂直系统脉冲产生部分 第一和第二面板，相位比较器和平滑元件。 第一面板水平系统脉冲产生部分和第二面板水平系统脉冲产生部分分别从信号VCOCLK 1生成第一面板水平系统输出组的参考信号和第二面板水平系统输出组的参考信号 从VCO输出。 因此，可以同时驱动两个不同的面板。
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公开(公告)号：US20050012531A1
公开(公告)日：2005-01-20
申请号：US10891230
申请日：2004-07-15
CPC分类号： H03K17/223
摘要： A power-on reset circuit of the present invention comprises: a first p-channel MOS transistor having the gate and the drain which are grounded and having a substrate which is connected to a power supply; a first resistor which is inserted and connected between the above-mentioned power supply and the source of the above-mentioned first p-channel MOS transistor; a first inverter having an input terminal which is connected to the source of the first p-channel MOS transistor; and a power-on reset signal output terminal which is connected to an output terminal of the first inverter.
摘要翻译： 本发明的上电复位电路包括：具有栅极和漏极的第一p沟道MOS晶体管，其接地并具有连接到电源的衬底; 插入并连接在上述电源和上述第一p沟道MOS晶体管的源极之间的第一电阻器; 第一反相器，具有连接到第一p沟道MOS晶体管的源极的输入端子; 以及连接到第一反相器的输出端子的上电复位信号输出端子。
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公开(公告)号：US07262646B2
公开(公告)日：2007-08-28
申请号：US10891230
申请日：2004-07-15
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A power-on reset circuit of the present invention comprises: a first p-channel MOS transistor having the gate and the drain which are grounded and having a substrate which is connected to a power supply; a first resistor which is inserted and connected between the above-mentioned power supply and the source of the above-mentioned first p-channel MOS transistor; a first inverter having an input terminal which is connected to the source of the first p-channel MOS transistor; and a power-on reset signal output terminal which is connected to an output terminal of the first inverter.
摘要翻译： 本发明的上电复位电路包括：具有栅极和漏极的第一p沟道MOS晶体管，其接地并具有连接到电源的衬底; 插入并连接在上述电源和上述第一p沟道MOS晶体管的源极之间的第一电阻器; 第一反相器，具有连接到第一p沟道MOS晶体管的源极的输入端子; 以及连接到第一反相器的输出端子的上电复位信号输出端子。
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公开(公告)号：US20080116983A1
公开(公告)日：2008-05-22
申请号：US11943227
申请日：2007-11-20
申请人： Norihide Kinugasa , Sachi Ota
发明人： Norihide Kinugasa , Sachi Ota
IPC分类号： H03L7/06
CPC分类号： H03L7/095
摘要： A PLL lock detection circuit produces a high precision PLL lock detection signal and enables eliminating a smoothing circuit. The PLL lock detection circuit reliably detects if the PLL circuit is locked reliably and without error by simultaneously evaluating both locked and unlocked states. A continuity detection unit detects if a PLL locked state continues for H consecutive periods, and another continuity detection unit detects if a PLL unlocked state continues for H consecutive periods. The continuity detection units simultaneously output the PLL locked/unlocked states, and an R-S latch holds the detection result.
摘要翻译： PLL锁定检测电路产生高精度PLL锁定检测信号，能够消除平滑电路。 PLL锁定检测电路通过同时评估锁定状态和解锁状态，可靠地检测PLL电路是否可靠且无错误地锁定。 连续性检测单元检测PLL锁定状态是否持续H个连续时段，另一个连续性检测单元检测PLL解锁状态是否持续H个连续时段。 连续性检测单元同时输出PLL锁定/解锁状态，R-S锁存器保持检测结果。
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8.发明申请SPIKE NOISE ELIMINATING CIRCUIT, DIGITAL SYSTEM USING THE SAME, AND IIC BUS 有权SPIKE噪声消除电路，使用它的数字系统和IIC总线公开(公告)号：US20100019838A1
公开(公告)日：2010-01-28
申请号：US12442649
申请日：2007-10-05
申请人： Norihide Kinugasa , Sachi Ota
发明人： Norihide Kinugasa , Sachi Ota
IPC分类号： H03K5/1252
CPC分类号： H03K5/1252
摘要： There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.
摘要翻译： 提供了一种尖峰噪声消除电路，其可以消除具有预定脉冲宽度或更小的可靠尖峰噪声，并且精确地发送和输出具有大于预定宽度的脉冲宽度的信号。 通过以下步骤来消除输入信号中的尖峰噪声：检测输入信号电平的一致性和通过将输入信号延迟最大待消除的噪声的脉冲宽度作为延迟量而获得的第一延迟信号; 并且基于作为检测到电平重合的结果获得的信号，对输入信号或通过将输入信号延迟一定时间段而获得的第二延迟信号进行采样。
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9.发明授权Spike noise eliminating circuit, digital system using the same, and IIC bus 有权尖峰噪声消除电路，使用数字系统和IIC总线公开(公告)号：US07868662B2
公开(公告)日：2011-01-11
申请号：US12442649
申请日：2007-10-05
申请人： Norihide Kinugasa , Sachi Ota
发明人： Norihide Kinugasa , Sachi Ota
IPC分类号： H03K5/00
CPC分类号： H03K5/1252
摘要： There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.
摘要翻译： 提供了一种尖峰噪声消除电路，其可以消除具有预定脉冲宽度或更小的可靠尖峰噪声，并且精确地发送和输出具有大于预定宽度的脉冲宽度的信号。 通过以下步骤来消除输入信号中的尖峰噪声：检测输入信号电平的一致性和通过将输入信号延迟最大待消除的噪声的脉冲宽度作为延迟量而获得的第一延迟信号; 并且基于作为检测到电平重合的结果获得的信号，对输入信号或通过将输入信号延迟一定时间段而获得的第二延迟信号进行采样。
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10.发明授权Horizontal shift clock pulse selecting circuit for driving a color LCD panel 有权用于驱动彩色LCD面板的水平移位时钟脉冲选择电路公开(公告)号：US07113161B2
公开(公告)日：2006-09-26
申请号：US10704153
申请日：2003-11-10
申请人： Yoshio Nirasawa , Yuji Amano , Norihide Kinugasa
发明人： Yoshio Nirasawa , Yuji Amano , Norihide Kinugasa
IPC分类号： G09G3/36
CPC分类号： G09G5/18 , G09G3/20 , G09G3/3611 , G09G2310/0224
摘要： An influence of a switching noise caused by a horizontal shift clock to an oscillation frequency of a voltage controlled oscillator should be eliminated, to prevent an image shift in a PAL skip period. For this purpose, an odd number line horizontal shift clock from an odd number line horizontal shift clock generator and an even number line horizontal shift clock from an even number line horizontal shift clock generator are switched by a horizontal shift clock switching circuit, to be input to a color LCD panel. The horizontal shift clock switching circuit selects and outputs either the odd number line horizontal shift clock or the even number line horizontal shift clock according to a line identifying signal, in a normal period. By contrast, in a PAL skip period a selecting state of the shift clock is inverted immediately upon start of a PAL skip period, from a selecting state right before the start of the skip period, and the selecting state is again inverted in half a cycle of a horizontal scanning period.
摘要翻译： 应该消除由水平移位时钟引起的开关噪声对压控振荡器的振荡频率的影响，以防止PAL跳跃期间的图像偏移。 为此，来自奇数行水平移位时钟发生器的奇数行水平移位时钟和来自偶数行水平移位时钟发生器的偶数行水平移位时钟由水平移位时钟切换电路切换为输入 到彩色液晶面板。 在正常周期中，水平移位时钟切换电路根据线路识别信号选择并输出奇数行水平移位时钟或偶数行水平移位时钟。 相反，在PAL跳过时段中，从跳过时段开始之前的选择状态开始，跳闸时钟的选择状态立即反转，并且选择状态在半个周期内再次反转 的水平扫描期间。
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