公开(公告)号：US5021883A

公开(公告)日：1991-06-04

申请号：US330551

申请日：1989-03-30

申请人： Noriya Sakamoto ,  Susumu Komatsu

发明人： Noriya Sakamoto ,  Susumu Komatsu

IPC分类号： H04N5/265 ,  H04N5/907 ,  H04N9/64

CPC分类号： H04N5/44504 ,  H04N9/641

摘要： An address control circuit for a video memory of a multi-image display system. The circuit includes a video signal source, a video memory for storing the video signal, an address holding circuit for controlling write addresses of the video memory which outputs address values during a video image period and holds address value corresponding to a start instance of a blanking period during the blanking period and a bias generating circuit for positioning address areas of the video memory in which the video signal is stored.

摘要翻译： 一种用于多图像显示系统的视频存储器的地址控制电路。 该电路包括视频信号源，用于存储视频信号的视频存储器，用于控制视频存储器的写入地址的地址保持电路，该视频存储器在视频图像周期期间输出地址值，并保持对应于消隐的开始实例的地址值 以及用于定位存储视频信号的视频存储器的地址区域的偏置产生电路。

公开(公告)号：US5440268A

公开(公告)日：1995-08-08

申请号：US306957

申请日：1994-09-16

申请人： Noboru Taga ,  Tatsuya Ishikawa ,  Susumu Komatsu

发明人： Noboru Taga ,  Tatsuya Ishikawa ,  Susumu Komatsu

IPC分类号： H04L27/22 ,  H04L27/00 ,  H04L27/233 ,  H03D3/00

CPC分类号： H04L27/2332 ,  H04L2027/0032 ,  H04L2027/0055 ,  H04L2027/0057 ,  H04L2027/0065 ,  H04L2027/0081

摘要： AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.

摘要翻译： 用于QPSK解调器的AFC电路，包括：通过将调制输入信号与来自正交相位本地振荡器的正交相关本地振荡频率信号相乘获得正交相关检测信号的电路，用于通过对检测信号进行采样将检测信号转换成相应的数字信号， 具有比输入信号的符号率高两倍的频率的正交相关时钟，用于使用符号定时采样值检测正交相关数字信号之间的频率误差的频率误差检测器和转换后的数字信号中的符号中间定时采样值 信号，第一有效性确定器，用于通过从符号定时之前和之后的采样值检测调制输入信号来确定频率误差信号是否有效以产生第一有效信号，第二有效性确定器用于确定 无论是 通过检测符号中间定时的绝对采样值来产生第一有效信号，以及用于提取频率误差信号的有效频率误差提取器作为用于控制振荡频率的频率控制信号， 当频率误差信号已经被第一和第二有效信号证明是有效的时，本地振荡器。

公开(公告)号：US5410573A

公开(公告)日：1995-04-25

申请号：US149005

申请日：1993-11-08

申请人： Noboru Taga ,  Tatsuya Ishikawa ,  Susumu Komatsu

发明人： Noboru Taga ,  Tatsuya Ishikawa ,  Susumu Komatsu

IPC分类号： H03L7/085 ,  H03L7/087 ,  H04L27/00 ,  H04L27/233 ,  H03D3/24

CPC分类号： H04L27/2332 ,  H03L7/087 ,  H03L2207/14 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0079

摘要： A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

摘要翻译： 一种数字锁相环，其包含相位比较器，其产生具有正弦相位比较特性而不是锯齿相位比较特性的相位偏差信号，以避免别名。

公开(公告)号：US07592942B2

公开(公告)日：2009-09-22

申请号：US12026673

申请日：2008-02-06

申请人： Susumu Komatsu ,  Masaki Nishikawa

发明人： Susumu Komatsu ,  Masaki Nishikawa

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  H03M1/0626 ,  H03M1/1225 ,  H04L27/206

摘要： An A/D conversion processing circuit includes: a switch sequentially switching over multiple inputs to select each thereof according to input bandwidth of the multiple inputs or fixedly selecting a single input; an A/D converter obtaining a digital signal through sampling on a switch output with a sampling frequency according to a necessary signal bandwidth; an interpolation section performing on each signal from a separation section which separates signals included in an A/D converter output, an interpolation processing according to a sampling timing deviation in the A/D converter, to obtain a signal where the multiple inputs are digitally converted at the same sampling timing; and an output section outputting as-is an output of the A/D converter if a signal of the single input is inputted to the A/D converter from the switch, thereby allowing commonly using a single A/D converter for multiple inputs, restraining increased circuit scale and power consumption.

摘要翻译： A / D转换处理电路包括：根据多个输入的输入带宽或固定地选择单个输入的顺序切换多个输入以选择每个输入的开关; A / D转换器，通过根据必要的信号带宽以采样频率通过开关输出采样获得数字信号; 内插部分，对来自A / D转换器输出中包含的信号的分离部分的每个信号执行根据A / D转换器中的采样定时偏差的内插处理，以获得多个输入被数字转换的信号 在相同的采样时间; 以及如果单个输入的信号从开关输入到A / D转换器，则原样输出A / D转换器的输出的输出部分，从而允许通常使用单个A / D转换器进行多个输入，约束 增加电路规模和功耗。

公开(公告)号：US20080191913A1

公开(公告)日：2008-08-14

申请号：US12026673

申请日：2008-02-06

申请人： Susumu Komatsu ,  Masaki Nishikawa

发明人： Susumu Komatsu ,  Masaki Nishikawa

IPC分类号： H03M1/00 ,  H03M1/60

CPC分类号： H03M1/0624 ,  H03M1/0626 ,  H03M1/1225 ,  H04L27/206

摘要： An A/D conversion processing circuit includes: a switch sequentially switching over multiple inputs to select each thereof according to input bandwidth of the multiple inputs or fixedly selecting a single input; an A/D converter obtaining a digital signal through sampling on a switch output with a sampling frequency according to a necessary signal bandwidth; an interpolation section performing on each signal from a separation section which separates signals included in an A/D converter output, an interpolation processing according to a sampling timing deviation in the A/D converter, to obtain a signal where the multiple inputs are digitally converted at the same sampling timing; and an output section outputting as-is an output of the A/D converter if a signal of the single input is inputted to the A/D converter from the switch, thereby allowing commonly using a single A/D converter for multiple inputs, restraining increased circuit scale and power consumption.

摘要翻译： A / D转换处理电路包括：根据多个输入的输入带宽或固定地选择单个输入的顺序切换多个输入以选择每个输入的开关; A / D转换器，通过根据必要的信号带宽以采样频率通过开关输出采样获得数字信号; 内插部分，对来自A / D转换器输出中包含的信号的分离部分的每个信号执行根据A / D转换器中的采样定时偏差的内插处理，以获得多个输入被数字转换的信号 在相同的采样时间; 以及如果单个输入的信号从开关输入到A / D转换器，则原样输出A / D转换器的输出的输出部分，从而允许通常使用单个A / D转换器进行多个输入，约束 增加电路规模和功耗。

公开(公告)号：US5051826A

公开(公告)日：1991-09-24

申请号：US486433

申请日：1990-02-28

申请人： Satoyuki Ishii ,  Susumu Komatsu

发明人： Satoyuki Ishii ,  Susumu Komatsu

IPC分类号： H04N7/01 ,  H04N5/14

CPC分类号： H04N5/142 ,  H04N7/012

摘要： A vertical edge detection circuit for a progressive scanning conversion circuit including an input circuit for receiving an interlaced scanning television signal, a first circuit for generating an intra-field difference signal from the interlaced scanning television signal, a second circuit for generating an inter-field difference signal from the interlaced scanning television signal and a third circuit for selectively outputting a maximum value one of the intra-field and inter-field difference signals.

摘要翻译： 一种用于逐行扫描转换电路的垂直边缘检测电路，包括用于接收隔行扫描电视信号的输入电路，用于从隔行扫描电视信号产生场内差分信号的第一电路，用于产生场间的第二电路 来自隔行扫描电视信号的差分信号和用于选择性地输出场内和场间差信号中的最大值之一的第三电路。