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    VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT
    2.
    发明申请
    VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT 有权

    公开(公告)号：US20160026195A1

    公开(公告)日：2016-01-28

    申请号：US14876332

    申请日：2015-10-06

    Applicant: Nvidia Corporation

    Inventor： Brian L. Smith ,  Stephen Felix ,  Jesse Max Guss ,  Tezaswi Raja

    IPC: G05F1/46

    CPC classification number: G05F1/465 ,  G05F1/462

    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

    Integrated circuit having an enhanced fuseless fuse structure, a method of manufacturing the same and a data structure for use with the fuseless fuse structure
    3.
    发明授权
    Integrated circuit having an enhanced fuseless fuse structure, a method of manufacturing the same and a data structure for use with the fuseless fuse structure 有权
    具有增强的无熔丝熔丝结构的集成电路，其制造方法和用于熔丝保险丝结构的数据结构

    公开(公告)号：US09230678B2

    公开(公告)日：2016-01-05

    申请号：US14153643

    申请日：2014-01-13

    Applicant: Nvidia Corporation

    Inventor： Sathish Jothikumar ,  Jesse Max Guss ,  Chen Hui

    IPC: G11C17/18 ,  G11C29/00

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/027 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402 ,  Y10T29/49155

    Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.

    Abstract translation: 本文提供了一种增强的无熔丝熔丝结构。 此外，本文公开了具有增强的无熔丝熔丝结构的IC，可以与该结构一起使用的数据结构和制造IC的方法。 在一个实施例中，IC包括：（1）熔丝封装件，被配置为解码用于控制熔丝的熔丝数据，（2）JTAG寄存器，被配置为将熔丝寄存器值存储在指定块中，其中熔丝寄存器值和指定块是 由无熔丝熔丝数据确定;（3）由软件配置的选项寄存器，用于存储用于修改熔丝寄存器值的保险丝覆盖数据。

    INTEGRATED CIRCUIT DETECTION CIRCUIT FOR A DIGITAL MULTI-LEVEL STRAP AND METHOD OF OPERATION THEREOF
    4.
    发明申请
    INTEGRATED CIRCUIT DETECTION CIRCUIT FOR A DIGITAL MULTI-LEVEL STRAP AND METHOD OF OPERATION THEREOF 审中-公开
    用于数字多级带的集成电路检测电路及其操作方法

    公开(公告)号：US20150219697A1

    公开(公告)日：2015-08-06

    申请号：US14173241

    申请日：2014-02-05

    Applicant: Nvidia Corporation

    Inventor： Victor Chen ,  Jesse Max Guss ,  Craig Ross ,  Kevin Wong ,  Jason Kwok-san Lee

    IPC: G01R19/165 ,  G06T1/20

    CPC classification number: G01R19/165 ,  H03K19/00 ,  H03K19/0002 ,  H04L25/00 ,  H04L25/065

    Abstract: An integrated circuit (IC) based detection circuit for determining a strap value and a method of detecting a digital strap value. In one embodiment, the detection circuit includes: (1) a first receiver including transistors having first electrical characteristics that define a first threshold for the first receiver, the first receiver operable to generate a first binary digit based on an input signal and the first threshold and (2) a second receiver including transistors having second electrical characteristics that differ from the first electrical characteristics and define a second threshold for the second receiver that is lower than the first threshold, the second receiver operable to generate a second binary digit based on the input signal and the second threshold, the first and second binary digits indicating whether the strap value lies above the first threshold, between the first and second thresholds or below the second threshold.

    Abstract translation: 一种用于确定条带值的基于集成电路（IC）的检测电路和一种检测数字带值的方法。 在一个实施例中，检测电路包括：（1）第一接收器，包括具有第一电特性的晶体管，第一电特性限定第一接收器的第一阈值，第一接收器可操作以基于输入信号和第一阈值产生第一二进制数字 和（2）第二接收器，包括具有不同于第一电特性的第二电特性的晶体管，并且限定低于第一阈值的第二接收器的第二阈值，第二接收器可操作以基于 输入信号和第二阈值，第一和第二二进制数字指示带值是否高于第一阈值，在第一和第二阈值之间或低于第二阈值。

    INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE
    5.
    发明申请
    INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE 有权
    具有增强的无熔丝结构的集成电路，其制造方法和使用无熔丝熔丝结构的数据结构

    公开(公告)号：US20150200020A1

    公开(公告)日：2015-07-16

    申请号：US14153643

    申请日：2014-01-13

    Applicant: Nvidia Corporation

    Inventor： Sathish Jothikumar ,  Jesse Max Guss ,  Chen Hui

    IPC: G11C17/18 ,  G11C17/16

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/027 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402 ,  Y10T29/49155

    Abstract: An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values.

    Abstract translation: 本文提供了一种增强的无熔丝熔丝结构。 此外，本文公开了具有增强的无熔丝熔丝结构的IC，可以与该结构一起使用的数据结构和制造IC的方法。 在一个实施例中，IC包括：（1）熔丝封装件，被配置为解码用于控制熔丝的熔丝数据，（2）JTAG寄存器，被配置为将熔丝寄存器值存储在指定块中，其中熔丝寄存器值和指定块是 由无熔丝熔丝数据确定;（3）由软件配置的选项寄存器，用于存储用于修改熔丝寄存器值的保险丝覆盖数据。

    Setting a PCIE Device ID
    6.
    发明授权
    Setting a PCIE Device ID 有权

    公开(公告)号：US09639494B2

    公开(公告)日：2017-05-02

    申请号：US14070147

    申请日：2013-11-01

    Applicant: NVIDIA CORPORATION

    Inventor： Jesse Max Guss ,  Philip Browning Johnson ,  Chris Marriott ,  Wojciech Jan Truty

    IPC: G06F13/20 ,  G06F11/22 ,  G06F13/40 ,  H01H85/04

    CPC classification number: G06F13/4072 ,  G06F11/22 ,  H01H85/04

    Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.

    Voltage optimization circuit and managing voltage margins of an integrated circuit
    7.
    发明授权
    Voltage optimization circuit and managing voltage margins of an integrated circuit 有权
    电压优化电路和管理集成电路的电压裕度

    公开(公告)号：US09182768B2

    公开(公告)日：2015-11-10

    申请号：US14149915

    申请日：2014-01-08

    Applicant: Nvidia Corporation

    Inventor： Brian L. Smith ,  Stephen Felix ,  Jesse Max Guss ,  Tezaswi Raja

    IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46

    CPC classification number: G05F1/465 ,  G05F1/462

    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

    Abstract translation: 这里公开了电压裕量控制器，包括IC的IC和控制IC的电压域的电压裕度的方法。 在一个实施例中，电压裕度控制器包括：（1）监视分支，包括电路功能指示器，其配置为指示电压域中的电路是否可在相应的候选降低的电压电平下工作，以及（2）耦合到监控分支的电压余量调整器， 被配置为基于电路功能指示器的操作数量来开发用于电压域的电压调节器的电压余量调整。

    VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT
    8.
    发明申请
    VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT 有权
    电压优化电路和集成电路的电压保护

    公开(公告)号：US20150192942A1

    公开(公告)日：2015-07-09

    申请号：US14149915

    申请日：2014-01-08

    Applicant: Nvidia Corporation

    Inventor： Brian L. Smith ,  Stephen Felix ,  Jesse Max Guss ,  Tezaswi Raja

    IPC: G05F1/46

    CPC classification number: G05F1/465 ,  G05F1/462

    Abstract: A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

    Abstract translation: 这里公开了电压裕量控制器，包括IC的IC和控制IC的电压域的电压裕度的方法。 在一个实施例中，电压裕度控制器包括：（1）监视分支，包括电路功能指示器，其配置为指示电压域中的电路是否可在相应的候选降低的电压电平下工作，以及（2）耦合到监控分支的电压余量调整器， 被配置为基于电路功能指示器的操作数量来开发用于电压域的电压调节器的电压余量调整。

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