公开(公告)号：US09007079B2

公开(公告)日：2015-04-14

申请号：US13667872

申请日：2012-11-02

Applicant: Nvidia Corporation

Inventor： Dushyant Narayen ,  Nerinder Singh ,  Gunaseelan Ponnuvel ,  Hemant Kumar ,  Luai Nasser ,  Craig Nishizaki

IPC: G01R31/26 ,  G01R31/30

CPC classification number: G01R31/3008

Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract translation: 一种IDDQ测试系统和方法，其在一个实施例中包括1）经验提取子系统，用于为给定的半导体器件设计产生IDDQ与温度模型，2）自动测试设备（ATE）测试子系统，可操作以获得测量的 以及实现给定半导体器件设计的特定半导体器件的测量温度（Tm）的IDDQ值（IDDQm），获得测量的IDDQ值（IDDQm）的5秒内获得的测量温度（Tm），以及3）缩放子系统 可操作以使用IDDQ对温度模型将测量温度（Tm）下的测量IDDQ值（IDDQm）缩放到所需温度（Td）下的补偿IDDQ值（IDDQc）。

公开(公告)号：US20140214342A1

公开(公告)日：2014-07-31

申请号：US13754781

申请日：2013-01-30

Applicant: NVIDIA CORPORATION

Inventor： Gunaseelan Ponnuvel ,  Keith Michael Katcher ,  Tsung-Chi Eddy Yang ,  Nerinder Singh

IPC: G01R31/28

CPC classification number: H01L22/14 ,  H01L22/20

Abstract: A system, method, and computer program product are provided for verifying sensitivity test program stability. A sensitivity test program including a set of tests is run on a plurality of integrated circuit die fabricated on a silicon wafer, where each test in the set of tests specifies a different set of operating parameters for structures within each integrated circuit die. Results of the sensitivity test program are received for each integrated circuit die and the results of the sensitivity test program are stored in shadow bins allocated within a memory, where each shadow bin corresponds to a different test in the set of tests. The results may be used to verify and optimize operating voltage and operating frequency of different tests in the production test program and wafer fabrication process sensitivity.

Abstract translation: 提供了一种用于验证灵敏度测试程序稳定性的系统，方法和计算机程序产品。 包括一组测试的灵敏度测试程序在制造在硅晶片上的多个集成电路芯片上运行，其中该组测试中的每个测试为每个集成电路管芯内的结构规定了不同的一组操作参数。 针对每个集成电路管芯接收灵敏度测试程序的结果，并将灵敏度测试程序的结果存储在分配在存储器内的影子箱中，其中每个影子箱对应于该组测试中的不同测试。 结果可用于验证和优化生产测试程序和晶圆制造工艺灵敏度中不同测试的工作电压和工作频率。

公开(公告)号：US20140125364A1

公开(公告)日：2014-05-08

申请号：US13667872

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Dushyant Narayen ,  Nerinder Singh ,  Gunaseelan Ponnuvel ,  Hemant Kumar ,  Luai Nasser ,  Craig Nishizaki

IPC: G01R31/26

CPC classification number: G01R31/3008

Abstract: An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.

Abstract translation: 一种IDDQ测试系统和方法，在一个实施例中，deg包括1）经验提取子系统，可操作以产生用于给定半导体器件设计的IDDQ对温度模型; 2）自动测试设备（ATE）测试子系统，可操作以获得 以及实现给定半导体器件设计的特定半导体器件的测量温度（Tm）的测量IDDQ值（IDDQm），获得测量的IDDQ值（IDDQm）后5秒内获得的测量温度（Tm），以及3）缩放 子系统可操作以使用IDDQ对温度模型将测量温度（Tm）下的测量IDDQ值（IDDQm）缩放到期望温度（Td）下的补偿IDDQ值（IDDQc）。