公开(公告)号：US20220240408A1

公开(公告)日：2022-07-28

申请号：US17155959

申请日：2021-01-22

Applicant: Nvidia Corporation

Inventor： Benjamin D. Faulkner ,  Mini Rawat ,  Tao Li ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy

IPC: H05K7/14 ,  G06T1/20 ,  G06F9/50

Abstract: A system to select graphics processing units (GPUs) to execute a task is disclosed. In at least one embodiment, GPUs are selected based on one or more task parameters and one or more fused parameters.

公开(公告)号：US12124308B2

公开(公告)日：2024-10-22

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F11/00 ,  G06F1/20 ,  G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F1/206 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/0793

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US20240094793A1

公开(公告)日：2024-03-21

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F11/0721 ,  G06F11/076

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US20220113784A1

公开(公告)日：2022-04-14

申请号：US17068123

申请日：2020-10-12

Applicant: NVIDIA Corporation

Inventor： Jonah Matthew Alben ,  Benjamin D. Faulkner ,  Tao Li ,  Mini Rawat ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3246

Abstract: Apparatuses, systems, and techniques to power balance multiple chips. In at least one embodiment, a system includes a plurality of processors having substantially equal performance capability and different power consumption capability, where a cumulative power consumption of the processors is not to exceed a system power threshold if each processor is operated at substantially peak performance.