公开(公告)号：US11971774B2

公开(公告)日：2024-04-30

申请号：US17069172

申请日：2020-10-13

Applicant: Nvidia Corporation

Inventor： Benjamin Faulkner ,  Mini Rawat ,  Sreedhar Narayanaswamy ,  Tom Li ,  Swanand Bindoo ,  Divya Ramakrishnan

IPC: G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3296 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F1/3296 ,  G06F1/28 ,  G06F9/5094 ,  G06T1/20

Abstract: A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget.

公开(公告)号：US20210294791A1

公开(公告)日：2021-09-23

申请号：US16826005

申请日：2020-03-20

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Shantanu K. Sarangi ,  Hemalkumar Chandrakant Doshi ,  Hari Unni Krishnan ,  Gunaseelan Ponnuvel ,  Brian Lawrence Smith

IPC: G06F16/23

Abstract: Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.

公开(公告)号：US20240095133A1

公开(公告)日：2024-03-21

申请号：US17903959

申请日：2022-09-06

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Benjamin D. Faulkner

IPC: G06F15/78 ,  G06F11/07

CPC classification number: G06F15/7882 ,  G06F11/0721 ,  G06F11/0751

Abstract: Apparatuses, systems, and techniques adjust a frequency at which a processor operates. In at least one embodiment, a frequency at which a processor operates is adjusted based, at least in part, on different cores of the processor performing one or more identical instructions.

公开(公告)号：US20220240408A1

公开(公告)日：2022-07-28

申请号：US17155959

申请日：2021-01-22

Applicant: Nvidia Corporation

Inventor： Benjamin D. Faulkner ,  Mini Rawat ,  Tao Li ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy

IPC: H05K7/14 ,  G06T1/20 ,  G06F9/50

Abstract: A system to select graphics processing units (GPUs) to execute a task is disclosed. In at least one embodiment, GPUs are selected based on one or more task parameters and one or more fused parameters.

公开(公告)号：US20250021149A1

公开(公告)日：2025-01-16

申请号：US18221619

申请日：2023-07-13

Applicant: NVIDIA Corporation

Inventor： Tejvansh Singh Soni ,  Xutong Li ,  Sreedhar Narayanaswamy ,  Chad Plummer ,  Pratikkumar Dilipkumar Patel ,  Tao Li

IPC: G06F1/28 ,  G06F1/3296

Abstract: A system includes a processing unit coupled with one or more switches via one or more links. The processing unit is to determine a total threshold power value associated with the processing unit and the one or more links and estimate a power consumption value associated with a switch of the one or more switches. The processing unit can also determine the power consumption value of the switch and a second power consumption value of the processing unit fail to satisfy the total power threshold value and responsive to determining the power consumption value and the second power consumption value fail to satisfy the total power threshold value, increase an amount of power supplied to the processing unit to satisfy the total power threshold value.

公开(公告)号：US20220113789A1

公开(公告)日：2022-04-14

申请号：US17069172

申请日：2020-10-13

Applicant: Nvidia Corporation

Inventor： Benjamin Faulkner ,  Mini Rawat ,  Sreedhar Narayanaswamy ,  Tom Li ,  Swanand Bindoo ,  Divya Ramakrishnan

IPC: G06F1/3296 ,  G06T1/20 ,  G06F1/28 ,  G06F9/50

Abstract: A datacenter power management system and method is disclosed. A plurality of computing units are enabled to operate at a second frequency, higher than a first frequency, in response to determining from respective power coefficients for these computing units, that a power level at this higher frequency remains below a power budget

公开(公告)号：US12124308B2

公开(公告)日：2024-10-22

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F11/00 ,  G06F1/20 ,  G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F1/206 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/0793

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US20240094796A1

公开(公告)日：2024-03-21

申请号：US17837354

申请日：2022-06-10

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Kyle John O'Shaughnessy ,  Pratikkumar Dilipkumar Patel ,  Chad R. Plummer ,  Benjamin D. Faulkner

IPC: G06F1/324 ,  G06F1/3237 ,  G06F1/3296

CPC classification number: G06F1/324 ,  G06F1/3237 ,  G06F1/3296

Abstract: Apparatuses, systems, and techniques to optimize performance of a processor group. In at least one embodiment, a method increases a processor's clock frequency based, at least in part, on performance of other processors in a group.

公开(公告)号：US20240094793A1

公开(公告)日：2024-03-21

申请号：US17848274

申请日：2022-06-23

Applicant: NVIDIA Corporation

Inventor： Benjamin D. Faulkner ,  Padmanabhan Kannan ,  Srinivasan Raghuraman ,  Peng Cheng Shen ,  Divya Ramakrishnan ,  Swanand Santosh Bindoo ,  Sreedhar Narayanaswamy ,  Amey Y. Marathe

IPC: G06F1/30 ,  G06F11/07

CPC classification number: G06F1/30 ,  G06F11/0721 ,  G06F11/076

Abstract: Apparatuses, systems, and techniques to optimize processor performance. In at least one embodiment, a method increases an operation voltage of one or more processors, based at least in part, on one or more error rates of the one or more processors.

公开(公告)号：US11494370B2

公开(公告)日：2022-11-08

申请号：US16826005

申请日：2020-03-20

Applicant: NVIDIA Corporation

Inventor： Sreedhar Narayanaswamy ,  Shantanu K. Sarangi ,  Hemalkumar Chandrakant Doshi ,  Hari Unni Krishnan ,  Gunaseelan Ponnuvel ,  Brian Lawrence Smith

IPC: G06F16/23 ,  G06F11/27 ,  G06F11/273

Abstract: Latency of in-system test (IST) execution for a hardware component of an in-field (deployed) computing platform may be reduced when a value of a physical operating parameter can be changed without rebooting the computing platform. A test (e.g., patterns or vectors) is executed for varying values of the physical operating parameter (e.g., supply voltage, clock speed, temperature, noise magnitude/duration, operating current, and the like), providing the ability to detect faults in the hardware components.