QUANTIZING LOOP MEMORY CELL SYSTEM

    公开(公告)号:US20210005249A1

    公开(公告)日:2021-01-07

    申请号:US17021675

    申请日:2020-09-15

    IPC分类号: G11C11/44 G11C11/16 G06N10/00

    摘要: One example includes a memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. The memory cell system also includes a bias element arranged in the quantizing loop and which is configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state.

    QUANTIZING LOOP MEMORY CELL SYSTEM
    2.
    发明申请

    公开(公告)号:US20200090738A1

    公开(公告)日:2020-03-19

    申请号:US16133305

    申请日:2018-09-17

    IPC分类号: G11C11/44 G11C11/16 G06N99/00

    摘要: One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

    RECIPROCAL QUANTUM LOGIC COMPARATOR FOR QUBIT READOUT
    3.
    发明申请
    RECIPROCAL QUANTUM LOGIC COMPARATOR FOR QUBIT READOUT 有权
    用于QUBIT READOUT的RECIPROCAL QUANTUM LOGIC COMPARATOR

    公开(公告)号:US20150254571A1

    公开(公告)日:2015-09-10

    申请号:US14202724

    申请日:2014-03-10

    IPC分类号: G06N99/00 H01L39/22

    摘要: One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.

    摘要翻译: 本发明的一个方面包括相互量子逻辑(RQL)读出系统。 该系统包括其上提供读取脉冲的输入级和被配置为传播输出脉冲的输出级。 该系统还包括RQL比较器,其包括耦合到量子位的第一约瑟夫逊结和第二约瑟夫逊结。 偏置电流在量子位的第一量子态的第一约瑟夫逊结和量子位的第二量子态之间切换第二约瑟夫逊结。 第一约瑟夫逊结触发器响应于读取脉冲在第一量子状态中在输出级上提供输出脉冲,并且第二约瑟夫逊结触发在第二量子态中在输出级上不响应读取而不提供输出脉冲 脉冲。

    JOSEPHSON TRANSMISSION LINE (JTL) SYSTEM
    4.
    发明申请

    公开(公告)号:US20170141769A1

    公开(公告)日:2017-05-18

    申请号:US14943767

    申请日:2015-11-17

    IPC分类号: H03K3/38 G06F1/04 H03K19/195

    摘要: One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.

    RECIPROCAL QUANTUM LOGIC COMPARATOR FOR QUBIT READOUT

    公开(公告)号:US20160156357A1

    公开(公告)日:2016-06-02

    申请号:US15008022

    申请日:2016-01-27

    IPC分类号: H03K19/195

    摘要: One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.

    JOSEPHSON MAGNETIC MEMORY CELL SYSTEM
    6.
    发明申请
    JOSEPHSON MAGNETIC MEMORY CELL SYSTEM 有权
    JOSEPHSON磁记忆体系统

    公开(公告)号:US20150043273A1

    公开(公告)日:2015-02-12

    申请号:US13485397

    申请日:2012-05-31

    IPC分类号: G11C11/44 G11C11/16

    摘要: One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

    摘要翻译: 本发明的一个方面包括约瑟夫森磁存储系统。 该系统包括传导读取电流的超导电极。 该系统还包括滞后磁性约瑟夫逊结(HMJJ)。 HMJJ可以存储二进制值,并将与流过HMJJ的读取电流相关联的超导对从单态状态转换为三态态。 该系统还包括磁耦合到HMJJ并被配置为响应于至少一个写入电流将二进制值写入到HMJJ中的写入电路和配置成响应于应用中确定存储在HMJJ中的二进制值的读取电路 读取电流到HMJJ。

    SUPERCONDUCTING BI-DIRECTIONAL CURRENT DRIVER

    公开(公告)号:US20190036515A1

    公开(公告)日:2019-01-31

    申请号:US16150045

    申请日:2018-10-02

    IPC分类号: H03K3/38 G11C7/12

    摘要: One example includes a superconducting bidirectional current driver. The current driver includes a first direction superconducting latch that is activated in response to a first activation signal to provide a first current path of an input current through a bidirectional current load in a first direction. The current driver also includes a second direction superconducting latch that is activated in response to a second activation signal to provide a second current path of the input current through the bidirectional current load in a second direction opposite the first direction.

    SUPERCONDUCTING SINGLE-POLE DOUBLE-THROW SWITCH SYSTEM
    9.
    发明申请
    SUPERCONDUCTING SINGLE-POLE DOUBLE-THROW SWITCH SYSTEM 有权
    超级单通双向开关系统

    公开(公告)号:US20160233860A1

    公开(公告)日:2016-08-11

    申请号:US14616451

    申请日:2015-02-06

    申请人: OFER NAAMAN

    发明人: OFER NAAMAN

    IPC分类号: H03K17/92

    CPC分类号: H03K17/92

    摘要: A superconducting switch system is provided that includes a filter network having a first SQUID coupled to a second SQUID via a common node, an input port coupled to the common node, a first output port coupled to the first SQUID, and a second output port coupled to the second SQUID. The superconducting switch system also includes a switch controller configured to control an amount of induced current through the first SQUID and the second SQUID to alternately switch the first and second SQUIDS between first inductance states in which a desired bandwidth portion of a signal provided at the input terminal passes to the first output terminal and is blocked from passing to the second output terminal, and second inductance states in which the desired bandwidth portion of the input signal passes to the second output terminal and is blocked from passing to the first output terminal.

    摘要翻译: 提供了一种超导开关系统,其包括具有经由公共节点耦合到第二SQUID的第一SQUID的滤波器网络,耦合到公共节点的输入端口,耦合到第一SQUID的第一输出端口和耦合到第二SQUID的第二输出端口 到第二个SQUID。 超导开关系统还包括开关控制器,该开关控制器被配置为控制通过第一SQUID和第二SQUID的感应电流的量,以在第一电感状态之间交替地切换第一和第二SQUIDS,其中在输入端提供的信号的期望带宽部分 终端传递到第一输出端并被阻止传递到第二输出端,以及第二电感状态,其中输入信号的期望带宽部分传递到第二输出端并被阻止传递到第一输出端。

    PARAMETRIC AMPLIFIER SYSTEM
    10.
    发明申请

    公开(公告)号:US20190131944A1

    公开(公告)日:2019-05-02

    申请号:US15799017

    申请日:2017-10-31

    IPC分类号: H03F19/00 H03F1/56

    摘要: One example includes a parametric amplifier system. The system includes an input/output (I/O) transmission line to propagate a signal tone. The system also includes a non-linearity circuit comprising at least one Josephson junction to provide at least one inductive path of the signal tone in parallel with the at least one Josephson junction. The system further includes an impedance matching network coupled to the I/O transmission line to provide impedance matching of the tone signal between the I/O transmission line and the non-linearity element.