公开(公告)号：US12047694B2

公开(公告)日：2024-07-23

申请号：US18051351

申请日：2022-10-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee

IPC: H04N25/46 ,  H01L27/146 ,  H04N25/587 ,  H04N25/771 ,  H04N25/779

CPC classification number: H04N25/46 ,  H01L27/14603 ,  H01L27/14614 ,  H04N25/587 ,  H04N25/771 ,  H04N25/779

Abstract: A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

公开(公告)号：US20240145501A1

公开(公告)日：2024-05-02

申请号：US18051437

申请日：2022-10-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14605 ,  H01L27/1463 ,  H01L27/14645

Abstract: A pixel array includes pixel circuits including a first pixel circuit having a first split floating diffusion receiving charge from first and third photodiodes through first and third transfer transistors, and a second split floating diffusion receiving the charge from second and fourth photodiodes through second and fourth transfer transistors. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits.

公开(公告)号：US20240147088A1

公开(公告)日：2024-05-02

申请号：US18051351

申请日：2022-10-31

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee

IPC: H04N25/587 ,  H01L27/146 ,  H04N25/11 ,  H04N25/771 ,  H04N25/779

CPC classification number: H04N25/587 ,  H01L27/14603 ,  H04N25/11 ,  H04N25/771 ,  H04N25/779

Abstract: A pixel array includes pixel circuits including a first pixel circuit having first and second split floating diffusions receiving charge from first and third photodiodes through first and third transfer transistors, and from second and fourth photodiodes through second and fourth transfer transistors, respectively. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits. A dual floating diffusion transistor is coupled between the first and second split floating diffusions and the third and fourth split floating diffusions to bin charges in the first, second, third, and fourth floating diffusions.

公开(公告)号：US11683602B1

公开(公告)日：2023-06-20

申请号：US17716856

申请日：2022-04-08

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Sangjoo Lee ,  Rui Wang ,  Xuelian Liu ,  Min Qu ,  Liang Zuo ,  Selcuk Sen ,  Hiroaki Ebihara ,  Lihang Fan

IPC: H04N25/615 ,  H04N25/133 ,  H04N25/13 ,  H04N25/447

CPC classification number: H04N25/6153 ,  H04N25/133 ,  H04N25/134 ,  H04N25/447

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.