公开(公告)号：US10572620B2

公开(公告)日：2020-02-25

申请号：US15667381

申请日：2017-08-02

Applicant: Oracle International Corporation

Inventor： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness ,  Johan Bastiaens

IPC: G06F17/50

Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

公开(公告)号：US20190042687A1

公开(公告)日：2019-02-07

申请号：US15667381

申请日：2017-08-02

Applicant: Oracle International Corporation

Inventor： David L. Toub ,  Larry B. Edwards ,  Terry L. Maness ,  Johan Bastiaens

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/74

Abstract: A method and apparatus for performing custom, piecewise digital layout generation is disclosed. The method comprises selecting, in a schematic of a digital circuit displayed in a digital circuit layout tool, a group of transistors and selecting one of a plurality of rows in a physical layout in which the group of transistors is to be placed. After the group of transistors is selected, the digital circuit layout tool may automatically place transistors of the group of transistors in the one of the plurality of rows of the physical layout. The method further comprises repeating selecting of additional groups of transistors, selecting from the plurality of rows, and automatically placing until all transistors of the digital circuit depicted as in the schematic have been placed for use in generating a physical layout plan for the first digital circuit.

公开(公告)号：US09036447B2

公开(公告)日：2015-05-19

申请号：US13719773

申请日：2012-12-19

Applicant: Oracle International Corporation

Inventor： Robert P. Masleid ,  Johan Bastiaens

IPC: G11C8/10 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

Abstract translation: 具有减少泄漏的解码器电路被配置为解码地址并驱动多个字线中的一个字线可以在预解码级，解码级和字线驱动级中用两高逻辑门来实现。 这样的解码器电路可以在字线驱动器级中包括配置为驱动多个字线中的一个字线的多个二极NOR门。 在一些实施例中，共享公共输入的两高逻辑门由多输出静态逻辑实现。

公开(公告)号：US20140169117A1

公开(公告)日：2014-06-19

申请号：US13719773

申请日：2012-12-19

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Robert P. Masleid ,  Johan Bastiaens

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

Abstract translation: 具有减少泄漏的解码器电路被配置为解码地址并驱动多个字线中的一个字线可以在预解码级，解码级和字线驱动级中用两高逻辑门来实现。 这样的解码器电路可以在字线驱动器级中包括配置为驱动多个字线中的一个字线的多个二极NOR门。 在一些实施例中，共享公共输入的两高逻辑门由多输出静态逻辑实现。