Abstract:
The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.
Abstract:
Systems, methods, and apparatus for generating data packets and testing a packet switching system are provided. For example, a data packet diagnostic system includes an input queuing subsystem comprising a set of data queues, an injecting unit, and a diagnostic unit. Each data queue is coupled with a separate functional read/write path and debug read/write path. The injecting unit injects test data packets into at least one of the data queues via its respective debug read/write path. The test packets can then be processed (e.g., routed) through a data packet processing environment. In some implementations, packets are communicated via the data packet processing environment back to the input queuing subsystem, where the diagnostic unit can read present contents of at least one of the data queues to determine whether the present contents satisfy a predetermined test profile according to the injected data packets.
Abstract:
The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.
Abstract:
Integrated circuit devices, methods, and other embodiments associated with power throttling with temperature sensing and activity feedback are described. In one embodiment, an integrated circuit device includes temperature sensing logic, activity sensing logic, comparison logic, and signal logic. The temperature sensing logic is configured to output a temperature signal indicative of a temperature of a selected region of the device. The activity sensing logic is configured to output an activity signal indicative of a level of activity of a selected device function. The mode selection logic is configured to select the temperature signal or the activity signal. The comparison logic is configured to compare the selected signal to a series of threshold levels and output a comparison result. The signal logic is configured to generate a throttle signal based on the comparison result. The throttle signal is used to control a frequency of operation of a selected device component.
Abstract:
Systems, methods, and apparatus for generating data packets and testing a packet switching system are provided. For example, a data packet diagnostic system includes an input queuing subsystem comprising a set of data queues, an injecting unit, and a diagnostic unit. Each data queue is coupled with a separate functional read/write path and debug read/write path. The injecting unit injects test data packets into at least one of the data queues via its respective debug read/write path. The test packets can then be processed (e.g., routed) through a data packet processing environment. In some implementations, packets are communicated via the data packet processing environment back to the input queuing subsystem, where the diagnostic unit can read present contents of at least one of the data queues to determine whether the present contents satisfy a predetermined test profile according to the injected data packets.