公开(公告)号：US09625983B2

公开(公告)日：2017-04-18

申请号：US14336026

申请日：2014-07-21

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jurgen M. Schulz ,  Vishak Chandrasekhar ,  Yu-Cheng Chiu

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: Integrated circuit devices, methods, and other embodiments associated with power throttling with temperature sensing and activity feedback are described. In one embodiment, an integrated circuit device includes temperature sensing logic, activity sensing logic, comparison logic, and signal logic. The temperature sensing logic is configured to output a temperature signal indicative of a temperature of a selected region of the device. The activity sensing logic is configured to output an activity signal indicative of a level of activity of a selected device function. The mode selection logic is configured to select the temperature signal or the activity signal. The comparison logic is configured to compare the selected signal to a series of threshold levels and output a comparison result. The signal logic is configured to generate a throttle signal based on the comparison result. The throttle signal is used to control a frequency of operation of a selected device component.

公开(公告)号：US20140310555A1

公开(公告)日：2014-10-16

申请号：US13861917

申请日：2013-04-12

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jurgen M. Schulz ,  Vishak Chandrasekhar ,  Wayne F. Seltzer ,  Brian J. McGee

IPC: G06F11/20

CPC classification number: G06F11/2002 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/2007 ,  H04L43/0823 ,  H04L49/557

Abstract: The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

Abstract translation: 所公开的实施例公开了在多域系统中执行物理域错误隔离和恢复的技术，其中多域系统包括两个或多个处理器芯片和为处理器芯片提供连接性和高速缓存一致性支持的一个或多个交换芯片 ，并且处理器芯片被分成两个或更多个不同的域。 在运行期间，其中一个开关芯片决定了多域系统中的故障。 交换芯片确定与故障相关联的始发域，然后将故障信号和起始域的标识符发送到其内部单元，其中一些执行清除操作，清除始发域的所有业务，而不影响其他 多域系统的域。

公开(公告)号：US09256500B2

公开(公告)日：2016-02-09

申请号：US13861917

申请日：2013-04-12

Applicant: Oracle International Corporation

Inventor： Jurgen M. Schulz ,  Vishak Chandrasekhar ,  Wayne F. Seltzer ,  Brian J. McGee

IPC: G06F11/00 ,  G06F11/20 ,  H04L12/26 ,  H04L12/939

CPC classification number: G06F11/2002 ,  G06F11/0724 ,  G06F11/0793 ,  G06F11/2007 ,  H04L43/0823 ,  H04L49/557

Abstract: The disclosed embodiments disclose techniques for performing physical domain error isolation and recovery in a multi-domain system, where the multi-domain system includes two or more processor chips and one or more switch chips that provide connectivity and cache-coherency support for the processor chips, and the processor chips are divided into two or more distinct domains. During operation, one of the switch chips determines a fault in the multi-domain system. The switch chip determines an originating domain that is associated with the fault, and then signals the fault and an identifier for the originating domain to its internal units, some of which perform clearing operations that clear out all traffic for the originating domain without affecting the other domains of the multi-domain system.

Abstract translation: 所公开的实施例公开了在多域系统中执行物理域错误隔离和恢复的技术，其中多域系统包括两个或多个处理器芯片和为处理器芯片提供连接性和高速缓存一致性支持的一个或多个交换芯片 ，并且处理器芯片被分成两个或更多个不同的域。 在运行期间，其中一个开关芯片决定了多域系统中的故障。 交换芯片确定与故障相关联的始发域，然后将故障信号和起始域的标识符发送到其内部单元，其中一些执行清除操作，清除始发域的所有业务，而不影响其他 多域系统的域。

公开(公告)号：US09608839B2

公开(公告)日：2017-03-28

申请号：US14527385

申请日：2014-10-29

Applicant: Oracle International Corporation

Inventor： Jurgen Schulz ,  Vishak Chandrasekhar ,  Yu-cheng Chiu

IPC: H04L12/423 ,  H04L12/24

CPC classification number: H04L12/423 ,  H04L41/0803

Abstract: A system, comprising: a first local controller (LC) having a first position in a ring network and comprising a first LC cycle counter; a second LC having a second position in the ring network and comprising a second LC cycle counter; and a central controller (CC) connected to the ring network and comprising: a data structure linking the first LC to the first position and linking the second LC to the second position; and a CC cycle counter.

公开(公告)号：US20160127147A1

公开(公告)日：2016-05-05

申请号：US14527385

申请日：2014-10-29

Applicant: Oracle International Corporation

Inventor： Jurgen Schulz ,  Vishak Chandrasekhar ,  Yu-cheng Chiu

IPC: H04L12/423 ,  H04L12/24

CPC classification number: H04L12/423 ,  H04L41/0803

Abstract: A system, comprising: a first local controller (LC) having a first position in a ring network and comprising a first LC cycle counter; a second LC having a second position in the ring network and comprising a second LC cycle counter; and a central controller (CC) connected to the ring network and comprising: a data structure linking the first LC to the first position and linking the second LC to the second position; and a CC cycle counter.

Abstract translation: 一种系统，包括：第一本地控制器（LC），其具有环网中的第一位置并且包括第一LC周期计数器; 第二LC，在所述环形网络中具有第二位置，并且包括第二LC循环计数器; 以及连接到所述环网的中央控制器（CC），包括：将所述第一LC连接到所述第一位置并将所述第二LC连接到所述第二位置的数据结构; 和一个CC循环计数器。