公开(公告)号：US20100325481A1

公开(公告)日：2010-12-23

申请号：US12446409

申请日：2006-10-20

申请人： Odi Dahan ,  Ori Goren ,  Yossy Neeman

发明人： Odi Dahan ,  Ori Goren ,  Yossy Neeman

IPC分类号： G06F11/20

CPC分类号： G06F11/2025 ,  G06F11/2035 ,  G06F11/2051

摘要： A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal.

摘要翻译： 一种用于提供核心冗余的设备和方法，所述设备包括：多个核心; 核心可操作单元，其适于指示所述多个核心中的每个核心的可操作性; 以及核心控制信号单元，其适于提供包括虚拟核心到物理核心映射信号和物理核心到虚拟核心映射信号的映射信号; 其中所述多个核心中的每个核心包括响应于至少一个映射信号的至少一个中断接口和交叉开关接口。

公开(公告)号：US20090172414A1

公开(公告)日：2009-07-02

申请号：US11993811

申请日：2005-06-22

申请人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

发明人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F11/00 ,  H04L9/06

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A device that includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device is characterized by including a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information.A method that includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method is characterized by receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

摘要翻译： 一种包括适于存储加密指令的第一存储器单元，适于执行解密指令的处理器，由所述处理器访问的第二存储器单元和解密单元的设备。 该设备的特征在于包括密钥数据库和密钥选择电路，其中密钥选择电路适于从密钥数据库中选择一个选择的解密密钥，用于解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法，包括接收加密指令的阶段; 以及由处理器执行解密指令。 该方法的特征在于，接收密钥选择信息，响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收的密钥选择信息，以及使用所选择的解密密钥解密加密指令。

公开(公告)号：US08397081B2

公开(公告)日：2013-03-12

申请号：US11993811

申请日：2005-06-22

申请人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

发明人： Odi Dahan ,  Ori Goren ,  Yehuda Shvager

IPC分类号： G06F11/30

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A device includes a first memory unit adapted to store encrypted instructions, a processor adapted to execute decrypted instructions, a second memory unit accessible by the processor, and a decryption unit. The device includes a key database and a key selection circuit, wherein the key selection circuit is adapted to select a selected decryption key from the key database for decrypting encrypted instructions. The selection is responsive to a fixed selection information stored within the integrated circuit and to received key selection information. A method includes a stage of receiving encrypted instructions; and executing decrypted instructions by a processor. The method includes receiving key selection information, selecting a selected decryption key out of a key database in response to fixed selection information and to the received key selection information, and decrypting encrypted instructions using the selected decryption key.

摘要翻译： 设备包括适于存储加密指令的第一存储器单元，适于执行解密指令的处理器，由处理器访问的第二存储器单元和解密单元。 所述设备包括密钥数据库和密钥选择电路，其中密钥选择电路适于从密钥数据库中选择所选择的解密密钥，以解密加密的指令。 该选择响应存储在集成电路内的固定选择信息和接收的键选择信息。 一种方法包括接收加密指令的阶段; 以及由处理器执行解密指令。 所述方法包括接收密钥选择信息，响应于固定选择信息从密钥数据库中选择所选择的解密密钥和接收到的密钥选择信息，以及使用所选择的解密密钥解密加密指令。

公开(公告)号：US20080256297A1

公开(公告)日：2008-10-16

申请号：US12094123

申请日：2005-11-17

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0851 ,  G06F12/0888

摘要： A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

摘要翻译： 一种包含连接到多个一级缓存单元的多个处理器的设备。 该设备还包括多端口高级缓存单元，其包括第一模块互连，第二模块互连，多个高级缓存路径; 而多个高级缓存路径包括多个可同时访问的交错高级缓存单元。 方便地，该设备还包括至少一个不可缓存的路径。 一种用于从高速缓存检索信息的方法，包括：通过多端口高级缓存单元的第一模块互连并发地接收检索信息的请求。 如果发生至少两个高级缓存命中，则该方法的特征在于从多个高级缓存路径中的至少两个路径提供信息，以及如果发生高级缓存未命中则经由第二模块互连提供信息。

公开(公告)号：US20100271091A1

公开(公告)日：2010-10-28

申请号：US12606195

申请日：2009-10-27

申请人： Yong WANG ,  Odi Dahan ,  Zheng Wu ,  Jianbin Zhao

发明人： Yong WANG ,  Odi Dahan ,  Zheng Wu ,  Jianbin Zhao

IPC分类号： H03L7/06

CPC分类号： H03H17/0219 ,  H03H17/0628

摘要： A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.

摘要翻译： 用于异步采样率转换中的快速跟踪和抖动改进的方法包括用于异步采样率转换（ASRC）设备的数字锁相环（DPLL）。 DPLL中的控制装置包括增益控制器，其以固定值设置和维持控制装置的两个分支的增益（Ki，Kp），从而能够通过DPLL搜索期望值以确定期望值的邻域 并且当样本数量达到预定数量时降低增益。 DPLL中的处理单元基于输入时钟，输出时钟和系统时钟生成并处理第一和第二输入信号。 使用两个分支处理第二个输入信号。 根据第一处理输入信号的改变状态，由两个分支产生的信号被重新对齐，使得由两个分支产生的信号在相同的输入时钟间隔中进行采样。

公开(公告)号：US08234452B2

公开(公告)日：2012-07-31

申请号：US12516742

申请日：2006-11-30

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F12/0835

摘要： A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

摘要翻译： 一种用于获取指令的设备和方法。 该设备包括适于执行指令的处理器; 适于存储指令的高级存储单元; 由处理器控制的直接存储器访问（DMA）控制器; 包括第一输入端口和第二输入端口的指令高速缓存器; 其中所述指令高速缓冲存储器适于响应于由所述处理器产生并经由所述第一输入端口接收的读取请求向所述处理器提供指令; 其中所述指令高速缓冲存储器还适于响应于由所述DMA控制器生成且经由所述第二输入端口接收的读请求从高级存储器单元获取指令。

公开(公告)号：US07415493B2

公开(公告)日：2008-08-19

申请号：US10508619

申请日：2002-11-01

申请人： Odi Dahan

发明人： Odi Dahan

IPC分类号： G06F17/17

CPC分类号： H03H17/0628

摘要： An adaptive proportional integral control loop determines a ratio of the input sampling rate to the output sampling rate for use in asynchronous sample rate conversion. An input counter counts input samples and its output is sampled at the output sampling rate by a latch. The output of the latch is passed through a closed loop circuit comprising variable gain and integrator sections.

摘要翻译： 自适应比例积分控制回路确定输入采样率与异步采样率转换中使用的输出采样率的比率。 输入计数器对输入采样进行计数，其输出采用锁存器的输出采样率进行采样。 锁存器的输出通过包括可变增益和积分器部分的闭环电路。

公开(公告)号：US08219761B2

公开(公告)日：2012-07-10

申请号：US12094123

申请日：2005-11-17

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0851 ,  G06F12/0888

摘要： A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

摘要翻译： 一种包含连接到多个一级缓存单元的多个处理器的设备。 该设备还包括多端口高级缓存单元，其包括第一模块互连，第二模块互连，多个高级缓存路径; 而多个高级缓存路径包括多个可同时访问的交错高级缓存单元。 方便地，该设备还包括至少一个不可缓存的路径。 一种用于从高速缓存检索信息的方法，包括：通过多端口高级缓存单元的第一模块互连并发地接收检索信息的请求。 如果发生至少两个高级缓存命中，则该方法的特征在于从多个高级缓存路径中的至少两个路径提供信息，以及如果发生高级缓存未命中则经由第二模块互连提供信息。

公开(公告)号：US08093933B2

公开(公告)日：2012-01-10

申请号：US12606195

申请日：2009-10-27

申请人： Yong Wang ,  Odi Dahan ,  Zheng Wu ,  Jianbin Zhao

发明人： Yong Wang ,  Odi Dahan ,  Zheng Wu ,  Jianbin Zhao

IPC分类号： H03L7/00 ,  G06F17/17

CPC分类号： H03H17/0219 ,  H03H17/0628

摘要： A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.

摘要翻译： 用于异步采样率转换中的快速跟踪和抖动改进的方法包括用于异步采样率转换（ASRC）设备的数字锁相环（DPLL）。 DPLL中的控制装置包括增益控制器，其以固定值设置和维持控制装置的两个分支的增益（Ki，Kp），从而能够通过DPLL搜索期望值以确定期望值的邻域 并且当样本数量达到预定数量时降低增益。 DPLL中的处理单元基于输入时钟，输出时钟和系统时钟生成并处理第一和第二输入信号。 使用两个分支处理第二个输入信号。 根据第一处理输入信号的改变状态，由两个分支产生的信号被重新对齐，使得由两个分支产生的信号在相同的输入时钟间隔中进行采样。

公开(公告)号：US20100070713A1

公开(公告)日：2010-03-18

申请号：US12516742

申请日：2006-11-30

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F12/0835

摘要： A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

摘要翻译： 一种用于获取指令的设备和方法。 该设备包括适于执行指令的处理器; 适于存储指令的高级存储单元; 由处理器控制的直接存储器访问（DMA）控制器; 包括第一输入端口和第二输入端口的指令高速缓存器; 其中所述指令高速缓冲存储器适于响应于由所述处理器产生并经由所述第一输入端口接收的读取请求向所述处理器提供指令; 其中所述指令高速缓冲存储器还适于响应于由所述DMA控制器生成且经由所述第二输入端口接收的读请求从高级存储器单元获取指令。